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[patch/mips] Purge (almost) address masks
- To: GDB Patches <gdb-patches at sourceware dot cygnus dot com>
- Subject: [patch/mips] Purge (almost) address masks
- From: Andrew Cagney <ac131313 at cygnus dot com>
- Date: Tue, 11 Jul 2000 19:23:27 +1000
FYI,
The attatched patch moves the mips specific command ``set mask-address''
to remote-mips.c. mips-tdep.c no longer (by default) tries to mask
32/64 bit addresses.
I've tested this against random simulators and the PMON targets more
testing is needed (I've also a few follow on patches to apply).
Andrew
Mon Jun 19 11:29:35 2000 Andrew Cagney <cagney@b1.cygnus.com>
* remote-mips.c (mips_request): Change all arguments to ULONGEST.
(mips_exit_debug, mips_resume, mips_initialize, mips_wait,
mips_fetch_registers, mips_store_registers, mips_fetch_word):
Update.
(mips_xfer_memory): When mask_address_p, mask MEMADDR down to just
32 bits.
(_initialize_remote_mips): Add ``set mask-address'' command.
* mips-tdep.c (_initialize_mips_tdep): Replace "set mask-address"
with "set mips mask-address". Implement using
add_set_auto_boolean_cmd.
(struct gdbarch_tdep): Add default_mask_address_p.
(mips_mask_address_p, show_mask_address): New functions.
(mips_addr_bits_remove): Use mips_mask_address_p() to determine if
masking is needed.
Index: mips-tdep.c
===================================================================
RCS file: /cvs/cvsfiles/devo/gdb/mips-tdep.c,v
retrieving revision 1.234
diff -p -r1.234 mips-tdep.c
*** mips-tdep.c 2000/07/10 15:09:49 1.234
--- mips-tdep.c 2000/07/11 08:56:25
*************** struct gdbarch_tdep
*** 128,133 ****
--- 129,135 ----
int mips_regs_have_home_p;
int mips_default_stack_argsize;
int gdb_target_is_mips64;
+ int default_mask_address_p;
};
#if GDB_MULTI_ARCH
*************** mips_register_convert_to_raw (virtual_ty
*** 470,476 ****
}
/* Should the upper word of 64-bit addresses be zeroed? */
! static int mask_address_p = 1;
/* Should call_function allocate stack space for a struct return? */
int
--- 469,514 ----
}
/* Should the upper word of 64-bit addresses be zeroed? */
! enum cmd_auto_boolean mask_address_var = CMD_AUTO_BOOLEAN_AUTO;
!
! static int
! mips_mask_address_p (void)
! {
! switch (mask_address_var)
! {
! case CMD_AUTO_BOOLEAN_TRUE:
! return 1;
! case CMD_AUTO_BOOLEAN_FALSE:
! return 0;
! break;
! case CMD_AUTO_BOOLEAN_AUTO:
! return gdbarch_tdep (current_gdbarch)->default_mask_address_p;
! default:
! internal_error ("mips_mask_address_p: bad switch");
! return -1;
! }
! }
!
! static void
! show_mask_address (char *cmd, int from_tty)
! {
! switch (mask_address_var)
! {
! case CMD_AUTO_BOOLEAN_TRUE:
! printf_filtered ("The 32 bit mips address mask is enabled\n");
! break;
! case CMD_AUTO_BOOLEAN_FALSE:
! printf_filtered ("The 32 bit mips address mask is disabled\n");
! break;
! case CMD_AUTO_BOOLEAN_AUTO:
! printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
! mips_mask_address_p () ? "enabled" : "disabled");
! break;
! default:
! internal_error ("show_mask_address: bad switch");
! break;
! }
! }
/* Should call_function allocate stack space for a struct return? */
int
*************** mips_addr_bits_remove (addr)
*** 1331,1337 ****
{
if (GDB_TARGET_IS_MIPS64)
{
! if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff))
{
/* This hack is a work-around for existing boards using
PMON, the simulator, and any other 64-bit targets that
--- 1378,1384 ----
{
if (GDB_TARGET_IS_MIPS64)
{
! if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
{
/* This hack is a work-around for existing boards using
PMON, the simulator, and any other 64-bit targets that
*************** mips_addr_bits_remove (addr)
*** 1340,1356 ****
hardware. Thus, the PC or SP are likely to have been
sign extended to all 1s by instruction sequences that
load 32-bit addresses. For example, a typical piece of
! code that loads an address is this: lui $r2, <upper 16
! bits> ori $r2, <lower 16 bits> But the lui sign-extends
! the value such that the upper 32 bits may be all 1s. The
! workaround is simply to mask off these bits. In the
! future, gcc may be changed to support true 64-bit
! addressing, and this masking will have to be disabled. */
addr &= (CORE_ADDR) 0xffffffff;
}
}
! else
{
/* Even when GDB is configured for some 32-bit targets
(e.g. mips-elf), BFD is configured to handle 64-bit targets,
so CORE_ADDR is 64 bits. So we still have to mask off
--- 1387,1408 ----
hardware. Thus, the PC or SP are likely to have been
sign extended to all 1s by instruction sequences that
load 32-bit addresses. For example, a typical piece of
! code that loads an address is this:
! lui $r2, <upper 16 bits>
! ori $r2, <lower 16 bits>
! But the lui sign-extends the value such that the upper 32
! bits may be all 1s. The workaround is simply to mask off
! these bits. In the future, gcc may be changed to support
! true 64-bit addressing, and this masking will have to be
! disabled. */
addr &= (CORE_ADDR) 0xffffffff;
}
}
! else if (mips_mask_address_p ())
{
+ /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
+ masking off bits, instead, the actual target should be asking
+ for the address to be converted to a valid pointer. */
/* Even when GDB is configured for some 32-bit targets
(e.g. mips-elf), BFD is configured to handle 64-bit targets,
so CORE_ADDR is 64 bits. So we still have to mask off
*************** search. The only need to set it is when
*** 5009,5020 ****
/* Allow the user to control whether the upper bits of 64-bit
addresses should be zeroed. */
! add_show_from_set
! (add_set_cmd ("mask-address", no_class, var_boolean, (char *) &mask_address_p,
! "Set zeroing of upper 32 bits of 64-bit addresses.\n\
! Use \"on\" to enable the masking, and \"off\" to disable it.\n\
! Without an argument, zeroing of upper address bits is enabled.", &setlist),
! &showlist);
/* Allow the user to control the size of 32 bit registers within the
raw remote packet. */
--- 4999,5011 ----
/* Allow the user to control whether the upper bits of 64-bit
addresses should be zeroed. */
! c = add_set_auto_boolean_cmd ("mask-address", no_class, &mask_address_var,
! "Set zeroing of upper 32 bits of 64-bit addresses.\n\
! Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
! the correct value.\n",
! &setmipscmdlist);
! add_cmd ("mask-address", no_class, show_mask_address,
! "Show current mask-address value", &showmipscmdlist);
/* Allow the user to control the size of 32 bit registers within the
raw remote packet. */
Index: remote-mips.c
===================================================================
RCS file: /cvs/cvsfiles/devo/gdb/remote-mips.c,v
retrieving revision 2.103
diff -p -r2.103 remote-mips.c
*** remote-mips.c 2000/06/17 14:01:45 2.103
--- remote-mips.c 2000/07/11 08:56:42
*************** static void mips_send_command (const cha
*** 77,85 ****
static int mips_receive_packet (char *buff, int throw_error, int timeout);
! static CORE_ADDR mips_request (int cmd, CORE_ADDR addr,
! CORE_ADDR data, int *perr, int timeout,
! char *buff);
static void mips_initialize (void);
--- 77,84 ----
static int mips_receive_packet (char *buff, int throw_error, int timeout);
! static ULONGEST mips_request (int cmd, ULONGEST addr, ULONGEST data,
! int *perr, int timeout, char *buff);
static void mips_initialize (void);
*************** mips_receive_packet (buff, throw_error,
*** 1247,1260 ****
occurs, it sets *PERR to 1 and sets errno according to what the
target board reports. */
! static CORE_ADDR
! mips_request (cmd, addr, data, perr, timeout, buff)
! int cmd;
! CORE_ADDR addr;
! CORE_ADDR data;
! int *perr;
! int timeout;
! char *buff;
{
char myBuff[DATA_MAXLEN + 1];
int len;
--- 1246,1258 ----
occurs, it sets *PERR to 1 and sets errno according to what the
target board reports. */
! static ULONGEST
! mips_request (int cmd,
! ULONGEST addr,
! ULONGEST data,
! int *perr,
! int timeout,
! char *buff)
{
char myBuff[DATA_MAXLEN + 1];
int len;
*************** mips_exit_debug ()
*** 1377,1391 ****
{
/* The DDB (NEC) and MiniRISC (LSI) versions of PMON exit immediately,
so we do not get a reply to this command: */
! mips_request ('x', (unsigned int) 0, (unsigned int) 0, NULL,
! mips_receive_wait, NULL);
mips_need_reply = 0;
if (!mips_expect (" break!"))
return -1;
}
else
! mips_request ('x', (unsigned int) 0, (unsigned int) 0, &err,
! mips_receive_wait, NULL);
if (!mips_expect (mips_monitor_prompt))
return -1;
--- 1375,1387 ----
{
/* The DDB (NEC) and MiniRISC (LSI) versions of PMON exit immediately,
so we do not get a reply to this command: */
! mips_request ('x', 0, 0, NULL, mips_receive_wait, NULL);
mips_need_reply = 0;
if (!mips_expect (" break!"))
return -1;
}
else
! mips_request ('x', 0, 0, &err, mips_receive_wait, NULL);
if (!mips_expect (mips_monitor_prompt))
return -1;
*************** mips_initialize ()
*** 1525,1532 ****
/* If this doesn't call error, we have connected; we don't care if
the request itself succeeds or fails. */
! mips_request ('r', (unsigned int) 0, (unsigned int) 0, &err,
! mips_receive_wait, NULL);
set_current_frame (create_new_frame (read_fp (), read_pc ()));
select_frame (get_current_frame (), 0);
}
--- 1521,1527 ----
/* If this doesn't call error, we have connected; we don't care if
the request itself succeeds or fails. */
! mips_request ('r', 0, 0, &err, mips_receive_wait, NULL);
set_current_frame (create_new_frame (read_fp (), read_pc ()));
select_frame (get_current_frame (), 0);
}
*************** mips_resume (pid, step, siggnal)
*** 1779,1787 ****
/* LSI PMON requires returns a reply packet "0x1 s 0x0 0x57f" after
a single step, so we wait for that. */
! mips_request (step ? 's' : 'c',
! (unsigned int) 1,
! (unsigned int) siggnal,
mips_monitor == MON_LSI && step ? &err : (int *) NULL,
mips_receive_wait, NULL);
}
--- 1774,1780 ----
/* LSI PMON requires returns a reply packet "0x1 s 0x0 0x57f" after
a single step, so we wait for that. */
! mips_request (step ? 's' : 'c', 1, siggnal,
mips_monitor == MON_LSI && step ? &err : (int *) NULL,
mips_receive_wait, NULL);
}
*************** mips_wait (pid, status)
*** 1836,1843 ****
/* No timeout; we sit here as long as the program continues to execute. */
mips_wait_flag = 1;
! rstatus = mips_request ('\000', (unsigned int) 0, (unsigned int) 0, &err, -1,
! buff);
mips_wait_flag = 0;
if (err)
mips_error ("Remote failure: %s", safe_strerror (errno));
--- 1829,1835 ----
/* No timeout; we sit here as long as the program continues to execute. */
mips_wait_flag = 1;
! rstatus = mips_request ('\000', 0, 0, &err, -1, buff);
mips_wait_flag = 0;
if (err)
mips_error ("Remote failure: %s", safe_strerror (errno));
*************** mips_fetch_registers (regno)
*** 2033,2043 ****
compiled without the 64bit register access commands. This
means we cannot get hold of the full register width. */
if (mips_monitor == MON_DDB)
! val = (unsigned) mips_request ('t', (unsigned int) pmon_reg,
! (unsigned int) 0, &err, mips_receive_wait, NULL);
else
! val = mips_request ('r', (unsigned int) pmon_reg,
! (unsigned int) 0, &err, mips_receive_wait, NULL);
if (err)
mips_error ("Can't read register %d: %s", regno,
safe_strerror (errno));
--- 2025,2035 ----
compiled without the 64bit register access commands. This
means we cannot get hold of the full register width. */
if (mips_monitor == MON_DDB)
! val = (unsigned) mips_request ('t', pmon_reg, 0,
! &err, mips_receive_wait, NULL);
else
! val = mips_request ('r', pmon_reg, 0,
! &err, mips_receive_wait, NULL);
if (err)
mips_error ("Can't read register %d: %s", regno,
safe_strerror (errno));
*************** mips_store_registers (regno)
*** 2077,2083 ****
return;
}
! mips_request ('R', (unsigned int) mips_map_regno (regno),
read_register (regno),
&err, mips_receive_wait, NULL);
if (err)
--- 2069,2075 ----
return;
}
! mips_request ('R', mips_map_regno (regno),
read_register (regno),
&err, mips_receive_wait, NULL);
if (err)
*************** mips_fetch_word (addr)
*** 2093,2106 ****
unsigned int val;
int err;
! /* FIXME! addr was cast to uint! */
! val = mips_request ('d', addr, (unsigned int) 0, &err,
! mips_receive_wait, NULL);
if (err)
{
/* Data space failed; try instruction space. */
! /* FIXME! addr was cast to uint! */
! val = mips_request ('i', addr, (unsigned int) 0, &err,
mips_receive_wait, NULL);
if (err)
mips_error ("Can't read address 0x%s: %s",
--- 2085,2095 ----
unsigned int val;
int err;
! val = mips_request ('d', addr, 0, &err, mips_receive_wait, NULL);
if (err)
{
/* Data space failed; try instruction space. */
! val = mips_request ('i', addr, 0, &err,
mips_receive_wait, NULL);
if (err)
mips_error ("Can't read address 0x%s: %s",
*************** mips_store_word (addr, val, old_contents
*** 2123,2136 ****
int err;
unsigned int oldcontents;
! oldcontents = mips_request ('D', addr, (unsigned int) val,
! &err,
mips_receive_wait, NULL);
if (err)
{
/* Data space failed; try instruction space. */
! oldcontents = mips_request ('I', addr,
! (unsigned int) val, &err,
mips_receive_wait, NULL);
if (err)
return errno;
--- 2112,2123 ----
int err;
unsigned int oldcontents;
! oldcontents = mips_request ('D', addr, val, &err,
mips_receive_wait, NULL);
if (err)
{
/* Data space failed; try instruction space. */
! oldcontents = mips_request ('I', addr, val, &err,
mips_receive_wait, NULL);
if (err)
return errno;
*************** mips_store_word (addr, val, old_contents
*** 2147,2152 ****
--- 2134,2141 ----
for a longword, since it transfers values in ASCII. We want the
byte values, so we have to swap the longword values. */
+ static int mask_address_p = 1;
+
static int
mips_xfer_memory (memaddr, myaddr, len, write, ignore)
CORE_ADDR memaddr;
*************** mips_xfer_memory (memaddr, myaddr, len,
*** 2155,2170 ****
int write;
struct target_ops *ignore;
{
! register int i;
/* Round starting address down to longword boundary. */
! register CORE_ADDR addr = memaddr & ~3;
/* Round ending address up; get number of longwords that makes. */
! register int count = (((memaddr + len) - addr) + 3) / 4;
/* Allocate buffer of that many longwords. */
! register char *buffer = alloca (count * 4);
- int status;
-
if (write)
{
/* Fill start and end extra bytes of buffer with existing data. */
--- 2144,2167 ----
int write;
struct target_ops *ignore;
{
! int i;
! CORE_ADDR addr;
! int count;
! char *buffer;
! int status;
!
! /* PMON targets do not cope well with 64 bit addresses. Mask the
! value down to 32 bits. */
! if (mask_address_p)
! memaddr &= (CORE_ADDR) 0xffffffff;
!
/* Round starting address down to longword boundary. */
! addr = memaddr & ~3;
/* Round ending address up; get number of longwords that makes. */
! count = (((memaddr + len) - addr) + 3) / 4;
/* Allocate buffer of that many longwords. */
! buffer = alloca (count * 4);
if (write)
{
/* Fill start and end extra bytes of buffer with existing data. */
*************** synchronize with the remote system. A v
*** 3713,3716 ****
--- 3710,3720 ----
add_com ("pmon <command>", class_obscure, pmon_command,
"Send a packet to PMON (must be in debug mode).");
+
+ add_show_from_set (add_set_cmd ("mask-address", no_class,
+ var_boolean, &mask_address_p,
+ "Set zeroing of upper 32 bits of 64-bit addresses when talking to PMON targets.\n\
+ Use \"on\" to enable the masking and \"off\" to disable it.\n",
+ &setlist),
+ &showlist);
}