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[patch/mips] More multi-arch
- To: GDB Patches <gdb-patches at sourceware dot cygnus dot com>
- Subject: [patch/mips] More multi-arch
- From: Andrew Cagney <ac131313 at cygnus dot com>
- Date: Fri, 07 Jul 2000 19:17:49 +1000
FYI,
I've checked in the attatched. It simply converts a few more MIPS
macros to multi-arch.
Andrew
Fri Jul 7 18:29:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
* config/mips/tm-mips.h (IEEE_FLOAT, SKIP_PROLOGUE,
SAVED_PC_AFTER_CALL, DECR_PC_AFTER_BREAK, BREAKPOINT_FROM_PC,
INNER_THAN): Macros.
* mips-tdep.c (mips_in_lenient_prologue): Delete function.
(mips32_skip_prologue, mips16_skip_prologue, mips_skip_prologue):
Remove ``lenient'' argument.
(mips_saved_pc_after_call): New function.
(mips_gdbarch_init): Initialize gdbarch members inner_than,
breakpoint_from_pc, decr_pc_after_break, ieee_float,
skip_prologue, saved_pc_after_call.
Index: mips-tdep.c
===================================================================
RCS file: /cvs/src/src/gdb/mips-tdep.c,v
retrieving revision 1.23
diff -p -r1.23 mips-tdep.c
*** mips-tdep.c 2000/07/06 23:17:32 1.23
--- mips-tdep.c 2000/07/07 09:14:43
*************** mips_step_skips_delay (pc)
*** 2841,2849 ****
This is a helper function for mips_skip_prologue. */
static CORE_ADDR
! mips32_skip_prologue (pc, lenient)
! CORE_ADDR pc; /* starting PC to search from */
! int lenient;
{
t_inst inst;
CORE_ADDR end_pc;
--- 2841,2847 ----
This is a helper function for mips_skip_prologue. */
static CORE_ADDR
! mips32_skip_prologue (CORE_ADDR pc)
{
t_inst inst;
CORE_ADDR end_pc;
*************** mips32_skip_prologue (pc, lenient)
*** 2937,2945 ****
This is a helper function for mips_skip_prologue. */
static CORE_ADDR
! mips16_skip_prologue (pc, lenient)
! CORE_ADDR pc; /* starting PC to search from */
! int lenient;
{
CORE_ADDR end_pc;
int extend_bytes = 0;
--- 2935,2941 ----
This is a helper function for mips_skip_prologue. */
static CORE_ADDR
! mips16_skip_prologue (CORE_ADDR pc)
{
CORE_ADDR end_pc;
int extend_bytes = 0;
*************** mips16_skip_prologue (pc, lenient)
*** 3051,3059 ****
delay slot of a non-prologue instruction). */
CORE_ADDR
! mips_skip_prologue (pc, lenient)
! CORE_ADDR pc;
! int lenient;
{
/* See if we can determine the end of the prologue via the symbol table.
If so, then return either PC, or the PC after the prologue, whichever
--- 3047,3053 ----
delay slot of a non-prologue instruction). */
CORE_ADDR
! mips_skip_prologue (CORE_ADDR pc)
{
/* See if we can determine the end of the prologue via the symbol table.
If so, then return either PC, or the PC after the prologue, whichever
*************** mips_skip_prologue (pc, lenient)
*** 3068,3095 ****
instructions. */
if (pc_is_mips16 (pc))
! return mips16_skip_prologue (pc, lenient);
else
! return mips32_skip_prologue (pc, lenient);
! }
!
! #if 0
! /* The lenient prologue stuff should be superseded by the code in
! init_extra_frame_info which looks to see whether the stores mentioned
! in the proc_desc have actually taken place. */
!
! /* Is address PC in the prologue (loosely defined) for function at
! STARTADDR? */
!
! static int
! mips_in_lenient_prologue (startaddr, pc)
! CORE_ADDR startaddr;
! CORE_ADDR pc;
! {
! CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1);
! return pc >= startaddr && pc < end_prologue;
}
- #endif
/* Determine how a return value is stored within the MIPS register
file, given the return type `valtype'. */
--- 3062,3071 ----
instructions. */
if (pc_is_mips16 (pc))
! return mips16_skip_prologue (pc);
else
! return mips32_skip_prologue (pc);
}
/* Determine how a return value is stored within the MIPS register
file, given the return type `valtype'. */
*************** mips_get_saved_register (raw_buffer, opt
*** 3930,3935 ****
--- 3906,3924 ----
*addrp = addr;
}
+ /* Immediately after a function call, return the saved pc.
+ Can't always go through the frames for this because on some machines
+ the new frame is not set up until the new function executes
+ some instructions. */
+
+ static CORE_ADDR
+ mips_saved_pc_after_call (struct frame_info *frame)
+ {
+
+ return read_register (RA_REGNUM);
+ }
+
+
static gdbarch_init_ftype mips_gdbarch_init;
static struct gdbarch *
mips_gdbarch_init (info, arches)
*************** mips_gdbarch_init (info, arches)
*** 4234,4239 ****
--- 4223,4236 ----
set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
+
+ set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+ set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
+ set_gdbarch_decr_pc_after_break (gdbarch, 0);
+ set_gdbarch_ieee_float (gdbarch, 1);
+
+ set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
+ set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
return gdbarch;
}
Index: config/mips/tm-mips.h
===================================================================
RCS file: /cvs/src/src/gdb/config/mips/tm-mips.h,v
retrieving revision 1.13
diff -p -r1.13 tm-mips.h
*** tm-mips.h 2000/06/12 04:35:39 1.13
--- tm-mips.h 2000/07/07 09:14:47
*************** struct value;
*** 47,55 ****
#define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
#endif
- /* Floating point is IEEE compliant */
- #define IEEE_FLOAT (1)
-
/* The name of the usual type of MIPS processor that is in the target
system. */
--- 47,52 ----
*************** CORE_ADDR mips_addr_bits_remove (CORE_AD
*** 69,117 ****
#define FUNCTION_START_OFFSET 0
- /* Advance PC across any function entry prologue instructions
- to reach some "real" code. */
-
- #define SKIP_PROLOGUE(pc) (mips_skip_prologue (pc, 0))
- extern CORE_ADDR mips_skip_prologue (CORE_ADDR addr, int lenient);
-
/* Return non-zero if PC points to an instruction which will cause a step
to execute both the instruction at PC and an instruction at PC+4. */
extern int mips_step_skips_delay (CORE_ADDR);
#define STEP_SKIPS_DELAY_P (1)
#define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
- /* Immediately after a function call, return the saved pc.
- Can't always go through the frames for this because on some machines
- the new frame is not set up until the new function executes
- some instructions. */
-
- #define SAVED_PC_AFTER_CALL(frame) read_register(RA_REGNUM)
-
/* Are we currently handling a signal */
extern int in_sigtramp (CORE_ADDR, char *);
#define IN_SIGTRAMP(pc, name) in_sigtramp(pc, name)
-
- /* Stack grows downward. */
-
- #define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
-
- /* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
- 16- or 32-bit breakpoint should be used. It returns a pointer
- to a string of bytes that encode a breakpoint instruction, stores
- the length of the string to *lenptr, and adjusts the pc (if necessary) to
- point to the actual memory location where the breakpoint should be
- inserted. */
-
- extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
- #define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
-
- /* Amount PC must be decremented by after a breakpoint.
- This is often the number of bytes in BREAKPOINT
- but not always. */
-
- #define DECR_PC_AFTER_BREAK 0
/* Say how long (ordinary) registers are. This is a piece of bogosity
used in push_word and a few other places; REGISTER_RAW_SIZE is the
--- 66,81 ----