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[binutils-gdb] Fix ARI warnings in aarch64-tdep.c
- From: Yao Qi <qiyao at sourceware dot org>
- To: gdb-cvs at sourceware dot org
- Date: 27 May 2015 10:43:36 -0000
- Subject: [binutils-gdb] Fix ARI warnings in aarch64-tdep.c
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5d98d3cd862ab5d463f71926788d52bf1b30ef79
commit 5d98d3cd862ab5d463f71926788d52bf1b30ef79
Author: Yao Qi <yao.qi@linaro.org>
Date: Wed May 27 11:29:24 2015 +0100
Fix ARI warnings in aarch64-tdep.c
This patch fixes some ARI warnings:
$ bash ./gdb/contrib/ari/gdb_ari.sh -Wall -Werror -Wari gdb/aarch64-tdep.c
gdb/aarch64-tdep.c:3009: code: Do not use &&, or || at the end of a line
gdb/aarch64-tdep.c:3010: code: Do not use &&, or || at the end of a line
gdb/aarch64-tdep.c:3413: code: Do not use &&, or || at the end of a line
gdb/aarch64-tdep.c:3460: code: Do not use &&, or || at the end of a line
This patch moves && from the end of line to the start of the line.
gdb:
2015-05-27 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_record_branch_except_sys): Split lines
before operator &&.
(aarch64_record_load_store): Likewise.
Diff:
---
gdb/ChangeLog | 6 ++++++
gdb/aarch64-tdep.c | 14 +++++++-------
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index a5aa56f..3f3d2eb 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,9 @@
+2015-05-27 Yao Qi <yao.qi@linaro.org>
+
+ * aarch64-tdep.c (aarch64_record_branch_except_sys): Split lines
+ before operator &&.
+ (aarch64_record_load_store): Likewise.
+
2015-05-26 Doug Evans <dje@google.com>
PR c++/18141, c++/18417.
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 8597497..8f1c7ef 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -3006,9 +3006,9 @@ aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
/* Exception generation instructions. */
if (insn_bits24_27 == 0x04)
{
- if (!bits (aarch64_insn_r->aarch64_insn, 2, 4) &&
- !bits (aarch64_insn_r->aarch64_insn, 21, 23) &&
- bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
+ if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
+ && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
+ && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
{
ULONGEST svc_number;
@@ -3410,8 +3410,8 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
}
}
/* Load/store register (register offset) instructions. */
- else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 &&
- insn_bits10_11 == 0x02 && insn_bit21)
+ else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
+ && insn_bits10_11 == 0x02 && insn_bit21)
{
if (record_debug)
{
@@ -3457,8 +3457,8 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
}
}
/* Load/store register (immediate and unprivileged) instructions. */
- else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 &&
- !insn_bit21)
+ else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
+ && !insn_bit21)
{
if (record_debug)
{