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[binutils-gdb] sim: sh: fix broken handling in DSR reg
- From: Michael Frysinger <vapier at sourceware dot org>
- To: gdb-cvs at sourceware dot org
- Date: 28 Mar 2015 21:46:07 -0000
- Subject: [binutils-gdb] sim: sh: fix broken handling in DSR reg
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=02131c7ff660a5ca08147899429e6e7780d737aa
commit 02131c7ff660a5ca08147899429e6e7780d737aa
Author: Mike Frysinger <vapier@gentoo.org>
Date: Sat Mar 28 14:55:11 2015 -0400
sim: sh: fix broken handling in DSR reg
A missing */ caused a case statement to be incorrect masked out which
also hide an error where the wrong value was being checked. Fix both.
Diff:
---
sim/sh/ChangeLog | 4 ++++
sim/sh/gencode.c | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog
index 3e0fff1..46b8e53 100644
--- a/sim/sh/ChangeLog
+++ b/sim/sh/ChangeLog
@@ -1,5 +1,9 @@
2015-03-28 Mike Frysinger <vapier@gentoo.org>
+ * gencode.c (ppi_gensim): Add missing */. Change case 4 to case 5.
+
+2015-03-28 Mike Frysinger <vapier@gentoo.org>
+
* Makefile.in (gencode): Add $(BUILD_CFLAGS), $(BUILD_LDFLAGS),
and $(WARN_CFLAGS).
* gencode.c: Include ctype.h, stdlib.h, string.h, and unistd.h.
diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c
index 0fb1b87..bcaeb6c 100644
--- a/sim/sh/gencode.c
+++ b/sim/sh/gencode.c
@@ -3359,11 +3359,11 @@ ppi_gensim (void)
printf (" DSR |= res_grd >> 7 & 1;\n");
printf (" case 2: /* Zero Value Mode */\n");
printf (" DSR |= DSR >> 6 & 1;\n");
- printf (" case 3: /* Overflow mode\n");
+ printf (" case 3: /* Overflow mode */\n");
printf (" DSR |= overflow >> 4;\n");
printf (" case 4: /* Signed Greater Than Mode */\n");
printf (" DSR |= DSR >> 7 & 1;\n");
- printf (" case 4: /* Signed Greater Than Or Equal Mode */\n");
+ printf (" case 5: /* Signed Greater Than Or Equal Mode */\n");
printf (" DSR |= greater_equal >> 7;\n");
printf (" }\n");
printf (" assign_z:\n");