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src/sim/bfin ChangeLog dv-bfin_uart.c dv-bfin_ ...
- From: vapier at sourceware dot org
- To: gdb-cvs at sourceware dot org
- Date: 14 May 2011 15:59:09 -0000
- Subject: src/sim/bfin ChangeLog dv-bfin_uart.c dv-bfin_ ...
CVSROOT: /cvs/src
Module name: src
Changes by: vapier@sourceware.org 2011-05-14 15:59:09
Modified files:
sim/bfin : ChangeLog dv-bfin_uart.c dv-bfin_uart.h
dv-bfin_uart2.c
Log message:
sim: bfin: implement loop back support in the UARTs
The UART has a LOOP_ENA bit in its MCR register where writes to the THR
go to the RBR. Implement support for this mode.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/bfin/ChangeLog.diff?cvsroot=src&r1=1.36&r2=1.37
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/bfin/dv-bfin_uart.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/bfin/dv-bfin_uart.h.diff?cvsroot=src&r1=1.2&r2=1.3
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/bfin/dv-bfin_uart2.c.diff?cvsroot=src&r1=1.5&r2=1.6