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src/sim/bfin ChangeLog bfin-sim.c
- From: vapier at sourceware dot org
- To: gdb-cvs at sourceware dot org
- Date: 24 Mar 2011 03:12:16 -0000
- Subject: src/sim/bfin ChangeLog bfin-sim.c
CVSROOT: /cvs/src
Module name: src
Changes by: vapier@sourceware.org 2011-03-24 03:12:16
Modified files:
sim/bfin : ChangeLog bfin-sim.c
Log message:
sim: bfin: update AV and AC ASTAT bits with acc negation
The Acc=-Acc insn can overflow or carry with edge values, so make sure
we update the ASTAT bits accordingly to match the hardware. Also fix
a thinko where we always updated AC0 even when working with A1 regs.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/bfin/ChangeLog.diff?cvsroot=src&r1=1.13&r2=1.14
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/bfin/bfin-sim.c.diff?cvsroot=src&r1=1.8&r2=1.9