src/sim/rx ChangeLog cpu.h gdb-if.c main.c mem ...

[dj at sourceware dot org]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	dj@sourceware.org	2010-07-29 18:41:29

Modified files:
	sim/rx         : ChangeLog cpu.h gdb-if.c main.c mem.c mem.h 
	                 rx.c 

Log message:
	[include/opcode]
	
	* rx.h (RX_Operand_Type): Add TwoReg.
	(RX_Opcode_ID): Remove ediv and ediv2.
	
	[opcodes]
	
	* rx-decode.opc (SRR): New.
	(rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
	r0,r0) and NOP3 (max r0,r0) special cases.
	* rx-decode.c: Regenerate.
	
	[sim/rx]
	
	* rx.c (decode_cache_base): New.
	(id_names): Remove ediv and edivu.
	(optype_names): Add TwoReg.
	(maybe_get_mem_page): New.
	(rx_get_byte): Call it.
	(get_op): Add TwoReg support.
	(put_op): Likewise.
	(PD, PS, PS2, GD, GS, GS2, DSZ, SSZ, S2SZ, US1, US2, OM): "opcode"
	is a pointer now.
	(DO_RETURN): New.  We use longjmp to return an exception result.
	(decode_opcode): Make opcode a pointer to the decode cache.  Save
	decoded opcode information and re-use.  Call DO_RETURN instead of
	return throughout.  Remove ediv and edivu.
	* mem.c (ptdc): New.  Adds decode cache.
	(rx_mem_ptr): Support it.
	(rx_mem_decode_cache): New.
	* mem.h (enum mem_ptr_action): add MPA_DECODE_CACHE.
	(rx_mem_decode_cache): Declare.
	* gdb-if.c (sim_resume): Add decode_opcode's setjmp logic here...
	* main.c (main): ...and here.  Use a fast loop if neither trace
	nor disassemble is given.
	* cpu.h (RX_MAKE_STEPPED, RX_MAKE_HIT_BREAK, RX_MAKE_EXITED,
	RX_MAKE_STOPPED, RX_EXITED, RX_STOPPED): Adjust so that 0 is not a
	valid code for anything.

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/ChangeLog.diff?cvsroot=src&r1=1.10&r2=1.11
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/cpu.h.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/gdb-if.c.diff?cvsroot=src&r1=1.7&r2=1.8
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/main.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/mem.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/mem.h.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/rx.c.diff?cvsroot=src&r1=1.5&r2=1.6