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src/sim common/ChangeLog common/sim-core.c m32 ...

CVSROOT:	/cvs/src
Module name:	src
Changes by:	nickc@sourceware.org	2003-12-19 11:43:57

Modified files:
	sim/common     : ChangeLog sim-core.c 
	sim/m32r       : ChangeLog Makefile.in configure configure.in 
	                 sim-if.c sim-main.h 
Added files:
	sim/m32r       : syscall.h traps-linux.c 

Log message:
	Add support for m32r-linux target, including a RELA ABI and PIC.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/ChangeLog.diff?cvsroot=src&r1=1.104&r2=1.105
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/common/sim-core.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/syscall.h.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/traps-linux.c.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/ChangeLog.diff?cvsroot=src&r1=1.18&r2=1.19
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/Makefile.in.diff?cvsroot=src&r1=1.9&r2=1.10
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/configure.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/configure.in.diff?cvsroot=src&r1=1.1.1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/sim-if.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/sim-main.h.diff?cvsroot=src&r1=1.5&r2=1.6
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