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[SCM] master: Mapping PPC32/64 registers to libunwing regs.
- From: jflavio at sourceware dot org
- To: frysk-cvs at sourceware dot org
- Date: 26 Nov 2007 04:37:19 -0000
- Subject: [SCM] master: Mapping PPC32/64 registers to libunwing regs.
- Reply-to: frysk at sourceware dot org
The branch, master has been updated
via 202ff1ef1dc5ae45101a21b83b1cd391226bbf9c (commit)
via 11f4195cccf704a492d800a7a0357aab90e3a077 (commit)
via 69e179214a09ba01ce3b6a9838c275d8aa228db5 (commit)
via dfebec25d6667fdc223c46b4e826dc24c682bc7a (commit)
via 0e9cde50f8e6b3237fd5415f55ac28d4284090df (commit)
from b583b959411d8b171488bcd8d1aaf10f596d878b (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 202ff1ef1dc5ae45101a21b83b1cd391226bbf9c
Author: Jose Flavio Aguilar Paulino <jflavio@br.ibm.com>
Date: Mon Nov 26 02:36:55 2007 -0200
Mapping PPC32/64 registers to libunwing regs.
commit 11f4195cccf704a492d800a7a0357aab90e3a077
Author: Jose Flavio Aguilar Paulino <jflavio@br.ibm.com>
Date: Mon Nov 26 02:34:37 2007 -0200
Removing string references to Registers.
commit 69e179214a09ba01ce3b6a9838c275d8aa228db5
Merge: dfebec25d6667fdc223c46b4e826dc24c682bc7a b583b959411d8b171488bcd8d1aaf10f596d878b
Author: Jose Flavio Aguilar Paulino <jflavio@br.ibm.com>
Date: Mon Nov 26 02:30:37 2007 -0200
Merge branch 'master' of ssh://sources.redhat.com/git/frysk
Conflicts:
frysk-core/frysk/proc/ChangeLog
commit dfebec25d6667fdc223c46b4e826dc24c682bc7a
Author: Jose Flavio Aguilar Paulino <jflavio@br.ibm.com>
Date: Mon Nov 26 02:10:53 2007 -0200
Removing references to registers by strings.
commit 0e9cde50f8e6b3237fd5415f55ac28d4284090df
Author: Jose Flavio Aguilar Paulino <jflavio@br.ibm.com>
Date: Mon Nov 26 02:07:30 2007 -0200
Patching PPC32 and PPC64 registers to ptrace.
-----------------------------------------------------------------------
Summary of changes:
frysk-core/frysk/isa/ChangeLog | 8 ++
frysk-core/frysk/isa/PPC32Registers.java | 72 +++++++++++--
frysk-core/frysk/isa/PPC64Registers.java | 113 +++++++++++++++-----
frysk-core/frysk/proc/ChangeLog | 6 +
frysk-core/frysk/proc/PPCBankRegisters.java | 56 ++++++----
frysk-core/frysk/stack/ChangeLog | 5 +
.../frysk/stack/LibunwindRegisterMapFactory.java | 75 +++++++++++++
frysk-core/frysk/util/ChangeLog | 7 ++
frysk-core/frysk/util/PPC32LinuxElfCorefile.java | 61 ++++++++---
frysk-core/frysk/util/PPC64LinuxElfCorefile.java | 54 ++++++++--
10 files changed, 379 insertions(+), 78 deletions(-)
First 500 lines of diff:
diff --git a/frysk-core/frysk/isa/ChangeLog b/frysk-core/frysk/isa/ChangeLog
index 66ed1aa..fe1e979 100644
--- a/frysk-core/frysk/isa/ChangeLog
+++ b/frysk-core/frysk/isa/ChangeLog
@@ -1,3 +1,11 @@
+2007-11-26 Jose Flavio Aguilar Paulino <joseflavio@gmail.com>
+
+ * PPC64Registers.java: Adding some ptrace registers, ordering the
+ registers like they are found in mcontext structure and adding
+ some comments to explain some special regs.
+
+ * PPC32Registers.java: Same as above.
+
2007-11-20 Jose Flavio Aguilar Paulino <jflavio@br.ibm>
* PPC64Registers.java: Renaming CR register to CCR,
diff --git a/frysk-core/frysk/isa/PPC32Registers.java b/frysk-core/frysk/isa/PPC32Registers.java
index f8f0ea2..2226ec8 100644
--- a/frysk-core/frysk/isa/PPC32Registers.java
+++ b/frysk-core/frysk/isa/PPC32Registers.java
@@ -47,6 +47,9 @@ import frysk.value.StandardTypes;
public class PPC32Registers extends Registers {
+ /*
+ * General Purpose Registers
+ */
public static final Register GPR0
= new Register("gpr0", StandardTypes.INT32B_T);
public static final Register GPR1
@@ -112,23 +115,67 @@ public class PPC32Registers extends Registers {
public static final Register GPR31
= new Register("gpr31", StandardTypes.INT32B_T);
- /* Special registers */
- public static final Register ARG
- = new Register("arg", StandardTypes.INT32B_T);
+ /*
+ * Special registers
+ */
+
+ /* Next instruction pointer register, this should
+ * not be used like in PPC64, instead, should use
+ * the link register (lr), but nip exists in ptrace */
+ public static final Register NIP
+ = new Register("nip", StandardTypes.INT32B_T);
+
+ /* Machine State Register */
+ public static final Register MSR
+ = new Register("msr", StandardTypes.INT32B_T);
+
+ /* Orig_R3, this is the content of the R3 which
+ * is lost when there is a system call (used to restart a syscall) */
+ public static final Register ORIGR3
+ = new Register("orig_r3", StandardTypes.INT32B_T);
/* Counter reg */
public static final Register CTR
= new Register("ctr", StandardTypes.INT32B_T);
+
+ /* Link Register
+ * (after a branch-and-link addr is saved here,
+ * to return from function calls) */
+ public static final Register LR
+ = new Register("lr", StandardTypes.VOIDPTR32B_T);
+
/* Fixed-point status and control register */
public static final Register XER
= new Register("xer", StandardTypes.INT32B_T);
+
+ /* Condition Code Register */
public static final Register CCR
= new Register("ccr", StandardTypes.INT32B_T);
- public static final Register LR
- = new Register("lr", StandardTypes.VOIDPTR32B_T);
- public static final Register FPSCR
- = new Register("fpscr", StandardTypes.INT32B_T);
+ /* Multiply-Quotient Register
+ (601 only (not used usually) */
+ public static final Register MQ
+ = new Register("mq", StandardTypes.VOIDPTR32B_T);
+
+ /* Trap (when ocourred) */
+ public static final Register TRAP
+ = new Register("trap", StandardTypes.INT32B_T);
+
+ /* DAR, Data Address Register */
+ public static final Register DAR
+ = new Register("dar", StandardTypes.VOIDPTR32B_T);
+
+ /* DSISR, Data Storage Interrupt Status Register */
+ public static final Register DSISR
+ = new Register("dsisr", StandardTypes.INT32B_T);
+
+ /* Result of a System call is stored by ptrace here */
+ public static final Register RESULT
+ = new Register("result", StandardTypes.INT32B_T);
+
+ /*
+ * Floating pointer registers
+ */
public static final Register FPR0
= new Register("fpr0", StandardTypes.FLOAT64B_T);
public static final Register FPR1
@@ -194,6 +241,13 @@ public class PPC32Registers extends Registers {
public static final Register FPR31
= new Register("fpr31", StandardTypes.FLOAT64B_T);
+ /* Floating Point Status and Control Register */
+ public static final Register FPSCR
+ = new Register("fpscr", StandardTypes.INT32B_T);
+
+ /*
+ * Defining Register Groups
+ */
public static final RegisterGroup GENERAL
= new RegisterGroup("general",
new Register[] {
@@ -204,7 +258,9 @@ public class PPC32Registers extends Registers {
public static final RegisterGroup SPECIAL
= new RegisterGroup("special",
- new Register[] { CTR, XER, CCR, LR, FPSCR });
+ new Register[] {
+ NIP, MSR, ORIGR3, CTR, LR, XER, CCR,
+ MQ, TRAP, DAR, DSISR, RESULT, FPSCR });
public static final RegisterGroup FLOATING_POINTER
= new RegisterGroup("floatingpointer",
diff --git a/frysk-core/frysk/isa/PPC64Registers.java b/frysk-core/frysk/isa/PPC64Registers.java
index e980166..ae2efff 100644
--- a/frysk-core/frysk/isa/PPC64Registers.java
+++ b/frysk-core/frysk/isa/PPC64Registers.java
@@ -1,7 +1,11 @@
// This file is part of the program FRYSK.
//
+// Copyright (C) 2006-2007 IBM
// Copyright 2007, Red Hat Inc.
//
+// Contributed by
+// Jose Flavio Aguilar Paulino <jflavio@br.ibm.com> <joseflavio@gmail.com>
+//
// FRYSK is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
@@ -43,6 +47,10 @@ import frysk.value.StandardTypes;
public class PPC64Registers extends Registers {
+ /*
+ * General Purpose Registers
+ */
+
public static final Register GPR0
= new Register("gpr0", StandardTypes.INT64B_T);
public static final Register GPR1
@@ -108,6 +116,67 @@ public class PPC64Registers extends Registers {
public static final Register GPR31
= new Register("gpr31", StandardTypes.INT64B_T);
+ /*
+ * Special registers
+ */
+
+ /* Next Instruction Pointer register */
+ public static final Register NIP
+ = new Register("nip", StandardTypes.INT64B_T);
+
+ /* Machine State Register */
+ public static final Register MSR
+ = new Register("msr", StandardTypes.INT64B_T);
+
+ /* Orig_R3, this is the content of the R3 which
+ * is lost when there is a system call (used to restart a syscall) */
+ public static final Register ORIGR3
+ = new Register("orig_r3", StandardTypes.INT64B_T);
+
+ /* Counter reg */
+ public static final Register CTR
+ = new Register("ctr", StandardTypes.INT64B_T);
+
+ /* Link Register
+ * (after a branch-and-link addr is saved here,
+ * to return from function calls) */
+ public static final Register LR
+ = new Register("lr", StandardTypes.VOIDPTR64B_T);
+
+ /* Fixed-point status and control register */
+ public static final Register XER
+ = new Register("xer", StandardTypes.INT64B_T);
+
+ /* Condition Code Register */
+ /* (In truth it is a 32 bit wide reg,
+ but usually it comes with padding for 64) */
+ public static final Register CCR
+ = new Register("ccr", StandardTypes.INT64B_T);
+
+ /* If software interrupts were enabled
+ (its a read only register used only by kernel) */
+ public static final Register SOFTE
+ = new Register("softe", StandardTypes.INT64B_T);
+
+ /* Trap (when ocourred) */
+ public static final Register TRAP
+ = new Register("trap", StandardTypes.INT64B_T);
+
+ /* DAR, Data Address Register */
+ public static final Register DAR
+ = new Register("dar", StandardTypes.VOIDPTR64B_T);
+
+ /* DSISR, Data Storage Interrupt Status Register */
+ public static final Register DSISR
+ = new Register("dsisr", StandardTypes.INT64B_T);
+
+ /* Result of a System call is stored by ptrace here */
+ public static final Register RESULT
+ = new Register("result", StandardTypes.INT64B_T);
+
+ /*
+ * Floating Pointer Registers
+ */
public static final Register FPR0
= new Register("fpr0", StandardTypes.FLOAT64B_T);
public static final Register FPR1
@@ -173,38 +242,29 @@ public class PPC64Registers extends Registers {
public static final Register FPR31
= new Register("fpr31", StandardTypes.FLOAT64B_T);
- /* Special Registers */
- public static final Register LR
- = new Register("lr", StandardTypes.VOIDPTR64B_T);
- public static final Register CTR
- = new Register("ctr", StandardTypes.INT64B_T);
- public static final Register ARG
- = new Register("arg", StandardTypes.INT64B_T);
- public static final Register CCR
- = new Register("ccr", StandardTypes.INT64B_T);
- public static final Register XER
- = new Register("xer", StandardTypes.INT64B_T);
+ /* Floating Point Status and Control Register
+ (In truth it is a 32 bit wide reg,
+ but usually it comes with padding for 64) */
+ public static final Register FPSCR
+ = new Register("fpscr", StandardTypes.INT32B_T);
- /* Alti-vec special register */
- public static final Register VRSAVE
- = new Register("vrsave", StandardTypes.INT64B_T);
+ /*
+ * Alti-vec special registers
+ */
public static final Register VSCR
= new Register("vscr", StandardTypes.INT64B_T);
+ public static final Register VRSAVE
+ = new Register("vrsave", StandardTypes.INT64B_T);
- /* SPUs special registers (for CELL processors) */
+ /*
+ * SPUs special registers
+ * (Cell-like processors)
+ */
public static final Register SPEACC
= new Register("speacc", StandardTypes.INT64B_T);
public static final Register SPEFSCR
= new Register("spefscr", StandardTypes.INT64B_T);
- /* Frame-Pointer */
- public static final Register FRP
- = new Register("frp", StandardTypes.VOIDPTR64B_T);
-
- /* Next-Instruction Pointer (Program Pointer) */
- public static final Register NIP
- = new Register("nip", StandardTypes.VOIDPTR64B_T);
-
/*
* Defining Register Groups
*/
@@ -218,9 +278,10 @@ public class PPC64Registers extends Registers {
public static final RegisterGroup SPECIAL
= new RegisterGroup("special",
- new Register[] { LR, CTR, ARG, CCR, XER,
- VRSAVE, VSCR, SPEACC, SPEFSCR,
- FRP, NIP });
+ new Register[] {
+ NIP, MSR, ORIGR3, CTR, LR, XER, CCR,
+ SOFTE, TRAP, FPSCR, DAR, DSISR, RESULT,
+ FPSCR, VRSAVE, VSCR, SPEACC, SPEFSCR });
public static final RegisterGroup FLOATING_POINTER
= new RegisterGroup("floatingpointer",
diff --git a/frysk-core/frysk/proc/ChangeLog b/frysk-core/frysk/proc/ChangeLog
index f451009..dc60cb5 100644
--- a/frysk-core/frysk/proc/ChangeLog
+++ b/frysk-core/frysk/proc/ChangeLog
@@ -1,3 +1,9 @@
+2007-11-26 Jose Flavio Aguilar Paulino <joseflavio@gmail.com>
+
+ * PPCBankRegisters.java: Removing "string" names for registers,
+ revised offsets of all registers (mainly floating pointer), for
+ PPC32 and PPC64.
+
2007-11-22 Andrew Cagney <cagney@redhat.com>
* X86BankRegisters.java (IA32_ON_X8664): Use
diff --git a/frysk-core/frysk/proc/PPCBankRegisters.java b/frysk-core/frysk/proc/PPCBankRegisters.java
index d6a9565..fe3ffd5 100644
--- a/frysk-core/frysk/proc/PPCBankRegisters.java
+++ b/frysk-core/frysk/proc/PPCBankRegisters.java
@@ -2,6 +2,9 @@
//
// Copyright 2006 IBM Corp.
// Copyright 2007 Red Hat Inc.
+//
+// Contributed by
+// Jose Flavio Aguilar Paulino (joseflavio@gmail.com)
//
// FRYSK is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by
@@ -79,19 +82,19 @@ public class PPCBankRegisters {
.add(new BankRegister(0, 116, 4, PPC32Registers.GPR29))
.add(new BankRegister(0, 120, 4, PPC32Registers.GPR30))
.add(new BankRegister(0, 124, 4, PPC32Registers.GPR31))
- .add(new BankRegister(0, 128, 4, "result"))
- .add(new BankRegister(0, 132, 4, "msr"))
- .add(new BankRegister(0, 136, 4, PPC32Registers.ARG)) //orig_r3
+ .add(new BankRegister(0, 128, 4, PPC32Registers.NIP)) //Fixme: PC I belive
+ .add(new BankRegister(0, 132, 4, PPC32Registers.MSR))
+ .add(new BankRegister(0, 136, 4, PPC32Registers.ORIGR3))
.add(new BankRegister(0, 140, 4, PPC32Registers.CTR))
.add(new BankRegister(0, 144, 4, PPC32Registers.LR))
.add(new BankRegister(0, 148, 4, PPC32Registers.XER))
.add(new BankRegister(0, 152, 4, PPC32Registers.CCR))
- .add(new BankRegister(0, 156, 4, PPC32Registers.FPSCR))
- .add(new BankRegister(0, 160, 4, "trap"))
- .add(new BankRegister(0, 164, 4, "dar"))
- .add(new BankRegister(0, 168, 4, "dsisr"))
- .add(new BankRegister(0, 172, 4, "mq"))
- .add(new BankRegister(0, 192, 8, PPC32Registers.FPR0))
+ .add(new BankRegister(0, 156, 4, PPC32Registers.MQ))
+ .add(new BankRegister(0, 160, 4, PPC32Registers.TRAP))
+ .add(new BankRegister(0, 164, 4, PPC32Registers.DAR))
+ .add(new BankRegister(0, 168, 4, PPC32Registers.DSISR))
+ .add(new BankRegister(0, 172, 4, PPC32Registers.RESULT))
+ .add(new BankRegister(0, 192, 8, PPC32Registers.FPR0)) // 48*4
.add(new BankRegister(0, 200, 8, PPC32Registers.FPR1))
.add(new BankRegister(0, 208, 8, PPC32Registers.FPR2))
.add(new BankRegister(0, 216, 8, PPC32Registers.FPR3))
@@ -123,6 +126,8 @@ public class PPCBankRegisters {
.add(new BankRegister(0, 424, 8, PPC32Registers.FPR29))
.add(new BankRegister(0, 432, 8, PPC32Registers.FPR30))
.add(new BankRegister(0, 440, 8, PPC32Registers.FPR31))
+ //There is a pad of 4 bytes before the FPSCR reg
+ .add(new BankRegister(0, 452, 4, PPC32Registers.FPSCR)) //(PT_FPR0 + 2*32 + 1)
;
public static final BankRegisterMap PPC64BE = new BankRegisterMap()
@@ -159,18 +164,18 @@ public class PPCBankRegisters {
.add(new BankRegister(0, 240, 8, PPC64Registers.GPR30))
.add(new BankRegister(0, 248, 8, PPC64Registers.GPR31))
.add(new BankRegister(0, 256, 8, PPC64Registers.NIP))
- .add(new BankRegister(0, 264, 8, "msr"))
- .add(new BankRegister(0, 272, 8, PPC64Registers.ARG)) //old orig_r3
+ .add(new BankRegister(0, 264, 8, PPC64Registers.MSR)) //in gdb: .ps_offset = 264
+ .add(new BankRegister(0, 272, 8, PPC64Registers.ORIGR3))
.add(new BankRegister(0, 280, 8, PPC64Registers.CTR))
.add(new BankRegister(0, 288, 8, PPC64Registers.LR))
.add(new BankRegister(0, 296, 8, PPC64Registers.XER))
.add(new BankRegister(0, 304, 8, PPC64Registers.CCR))
- .add(new BankRegister(0, 312, 8, "softe"))
- .add(new BankRegister(0, 320, 8, "trap"))
- .add(new BankRegister(0, 328, 8, "dar"))
- .add(new BankRegister(0, 336, 8, "dsisr"))
- .add(new BankRegister(0, 344, 8, "result"))
- .add(new BankRegister(0, 384, 8, PPC64Registers.FPR0))
+ .add(new BankRegister(0, 312, 8, PPC64Registers.SOFTE))
+ .add(new BankRegister(0, 320, 8, PPC64Registers.TRAP))
+ .add(new BankRegister(0, 328, 8, PPC64Registers.DAR))
+ .add(new BankRegister(0, 336, 8, PPC64Registers.DSISR))
+ .add(new BankRegister(0, 344, 8, PPC64Registers.RESULT))
+ .add(new BankRegister(0, 384, 8, PPC64Registers.FPR0)) //PT_FPR0 48
.add(new BankRegister(0, 392, 8, PPC64Registers.FPR1))
.add(new BankRegister(0, 400, 8, PPC64Registers.FPR2))
.add(new BankRegister(0, 408, 8, PPC64Registers.FPR3))
@@ -202,7 +207,15 @@ public class PPCBankRegisters {
.add(new BankRegister(0, 616, 8, PPC64Registers.FPR29))
.add(new BankRegister(0, 624, 8, PPC64Registers.FPR30))
.add(new BankRegister(0, 632, 8, PPC64Registers.FPR31))
- ;
+ .add(new BankRegister(0, 640, 4, PPC64Registers.FPSCR))
+ // Fixme: need to implement altivec registers
+ // Vector Registers are 128 bit wide
+ //.add(new BankRegister(0, 656, 16, PPC64Registers.VR0)) PT_VR0 82
+ //...
+ //.add(new BankRegister(0, 1152, 16, PPC64Registers.V31)) PT_VR0 + 31*2), index 148
+ //Need to put a 8 bytes pad here, because VSCR is 8 byte wide only
+ .add(new BankRegister(0, 1176, 8, PPC64Registers.VSCR)) // PT_VSCR (PT_VR0 + 32*2 + 1), index 147
+ .add(new BankRegister(0, 1184, 8, PPC64Registers.VRSAVE)); // PT_VRSAVE (PT_VR0 + 33*2), index 148
public static final BankRegisterMap PPC32BE_ON_PPC64BE
= new IndirectBankRegisterMap(ByteOrder.BIG_ENDIAN,
@@ -239,10 +252,10 @@ public class PPCBankRegisters {
.add("gpr29")
.add("gpr30")
.add("gpr31")
- .add("result")
+ .add("nip")
.add("msr")
- .add("arg")
- .add("ctr")
+ .add("orig_r3")
+ .add("ctr")
.add("lr")
.add("xer")
.add("ccr")
@@ -281,5 +294,6 @@ public class PPCBankRegisters {
.add("fpr29")
.add("fpr30")
.add("fpr31")
+ .add("fpscr")
;
}
diff --git a/frysk-core/frysk/stack/ChangeLog b/frysk-core/frysk/stack/ChangeLog
index 514e3fa..322be9e 100644
--- a/frysk-core/frysk/stack/ChangeLog
+++ b/frysk-core/frysk/stack/ChangeLog
@@ -1,3 +1,8 @@
+2007-11-26 Jose Flavio Aguilar Paulino <joseflavio@gmail.com>
+
+ * LibunwindRegisterMapFactory.java: Adding the correct map to
+ PPC32 and PPC64 from libunwind. Still missing special registers.
+
2007-11-23 Sami Wagiaalla <swagiaal@redhat.com>
* Frame.java (toPrint): Removed printlibrary boolean argument.
diff --git a/frysk-core/frysk/stack/LibunwindRegisterMapFactory.java b/frysk-core/frysk/stack/LibunwindRegisterMapFactory.java
index 7237360..e793fd2 100644
--- a/frysk-core/frysk/stack/LibunwindRegisterMapFactory.java
+++ b/frysk-core/frysk/stack/LibunwindRegisterMapFactory.java
@@ -42,8 +42,12 @@ package frysk.stack;
import frysk.isa.RegisterMap;
import lib.unwind.UnwindRegistersX86;
import lib.unwind.UnwindRegistersX8664;
+import lib.unwind.UnwindRegistersPPC32;
+import lib.unwind.UnwindRegistersPPC64;
import frysk.isa.ISA;
import frysk.isa.IA32Registers;
+import frysk.isa.PPC32Registers;
+import frysk.isa.PPC64Registers;
import frysk.isa.X8664Registers;
import frysk.isa.X87Registers;
import frysk.isa.ISAMap;
@@ -113,11 +117,82 @@ public class LibunwindRegisterMapFactory {
.add(X8664Registers.RIP, UnwindRegistersX8664.RIP)
;
+ private static final RegisterMap PPC64 = new RegisterMap()
+ .add(PPC64Registers.GPR0, UnwindRegistersPPC64.R0)
+ .add(PPC64Registers.GPR1, UnwindRegistersPPC64.R1)
+ .add(PPC64Registers.GPR2, UnwindRegistersPPC64.R2)
+ .add(PPC64Registers.GPR3, UnwindRegistersPPC64.R3)
+ .add(PPC64Registers.GPR4, UnwindRegistersPPC64.R4)
+ .add(PPC64Registers.GPR5, UnwindRegistersPPC64.R5)
+ .add(PPC64Registers.GPR6, UnwindRegistersPPC64.R6)
+ .add(PPC64Registers.GPR7, UnwindRegistersPPC64.R7)
+ .add(PPC64Registers.GPR8, UnwindRegistersPPC64.R8)
+ .add(PPC64Registers.GPR9, UnwindRegistersPPC64.R9)
+ .add(PPC64Registers.GPR10, UnwindRegistersPPC64.R10)
+ .add(PPC64Registers.GPR11, UnwindRegistersPPC64.R11)
+ .add(PPC64Registers.GPR12, UnwindRegistersPPC64.R12)
+ .add(PPC64Registers.GPR13, UnwindRegistersPPC64.R13)
+ .add(PPC64Registers.GPR14, UnwindRegistersPPC64.R14)
+ .add(PPC64Registers.GPR15, UnwindRegistersPPC64.R15)
+ .add(PPC64Registers.GPR16, UnwindRegistersPPC64.R16)
+ .add(PPC64Registers.GPR17, UnwindRegistersPPC64.R17)
+ .add(PPC64Registers.GPR18, UnwindRegistersPPC64.R18)
+ .add(PPC64Registers.GPR19, UnwindRegistersPPC64.R19)
+ .add(PPC64Registers.GPR20, UnwindRegistersPPC64.R20)
+ .add(PPC64Registers.GPR21, UnwindRegistersPPC64.R21)
+ .add(PPC64Registers.GPR22, UnwindRegistersPPC64.R22)
+ .add(PPC64Registers.GPR23, UnwindRegistersPPC64.R23)
+ .add(PPC64Registers.GPR24, UnwindRegistersPPC64.R24)
+ .add(PPC64Registers.GPR25, UnwindRegistersPPC64.R25)
+ .add(PPC64Registers.GPR26, UnwindRegistersPPC64.R26)
+ .add(PPC64Registers.GPR27, UnwindRegistersPPC64.R27)
+ .add(PPC64Registers.GPR28, UnwindRegistersPPC64.R28)
+ .add(PPC64Registers.GPR29, UnwindRegistersPPC64.R29)
+ .add(PPC64Registers.GPR30, UnwindRegistersPPC64.R30)
+ .add(PPC64Registers.GPR29, UnwindRegistersPPC64.R31)
+ ;
+
+ private static final RegisterMap PPC32 = new RegisterMap()
+ .add(PPC32Registers.GPR0, UnwindRegistersPPC32.R0)
+ .add(PPC32Registers.GPR1, UnwindRegistersPPC32.R1)
+ .add(PPC32Registers.GPR2, UnwindRegistersPPC32.R2)
+ .add(PPC32Registers.GPR3, UnwindRegistersPPC32.R3)
+ .add(PPC32Registers.GPR4, UnwindRegistersPPC32.R4)
+ .add(PPC32Registers.GPR5, UnwindRegistersPPC32.R5)
+ .add(PPC32Registers.GPR6, UnwindRegistersPPC32.R6)
hooks/post-receive
--
frysk system monitor/debugger