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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.
- From: bugzilla-daemon at bugs dot ecos dot sourceware dot org
- To: ecos-patches at ecos dot sourceware dot org
- Date: Sat, 18 May 2013 19:37:10 +0000
- Subject: [Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.
- Auto-submitted: auto-generated
- References: <bug-1001815-104 at http dot bugs dot ecos dot sourceware dot org/>
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Ilija Kocho <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Depends on| |1001838
--- Comment #7 from Ilija Kocho <ilijak@siva.com.mk> ---
In addition the CDL part attachment 2237 complements attachment 2226 of bug
1001838
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