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AT91SAM7S without crystal
- From: "James G. Smith" <jsmith at rallysmith dot co dot uk>
- To: ecos-patches at sources dot redhat dot com
- Date: Fri, 09 May 2008 11:16:54 +0100
- Subject: AT91SAM7S without crystal
Very minor tweak to support AT91SAM7S boards that do not use a crystal
to provide the main clock along with a new CDL option to select the
feature (defaults to CRYSTAL). In reality the wait loop after the
CKGR_MOR setting using OSCBYPASS is not needed since the status bit is
forced in such a configuration.
Diff against the CVS tree as of 11:00 20080509.
-- Jamie
P.S. Also tweaked the flash wait-state setting code to avoid unnecessary
instructions when clocks greater than 60MHz used since I spotted that
when adding the clock setup change.
Index: cdl/hal_arm_at91sam7s.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl,v
retrieving revision 1.8
diff -u -r1.8 hal_arm_at91sam7s.cdl
--- cdl/hal_arm_at91sam7s.cdl 1 May 2008 10:50:27 -0000 1.8
+++ cdl/hal_arm_at91sam7s.cdl 9 May 2008 10:11:39 -0000
@@ -223,7 +223,15 @@
legal_values { 3000000 to 20000000}
default_value { 18432000 }
description "
- What frequency of crystal is clocking the device."
+ The frequency clocking the device."
+ }
+
+ cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_TYPE {
+ display "Type of main frequency input"
+ flavor data
+ default_value { "CRYSTAL" }
+ legal_values { "CRYSTAL" "EXTCLOCK" }
+ description "Whether a crystal or a XIN input clock is clocking the device."
}
cdl_option CYGNUM_HAL_ARM_AT91_PLL_DIVIDER {
Index: include/hal_platform_setup.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h,v
retrieving revision 1.3
diff -u -r1.3 hal_platform_setup.h
--- include/hal_platform_setup.h 23 Apr 2008 08:17:44 -0000 1.3
+++ include/hal_platform_setup.h 9 May 2008 10:11:39 -0000
@@ -62,11 +62,11 @@
ldr r0,=AT91_MC
#if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 30000000
// When the clock is running faster than 30MHz we need a wait state
- ldr r1,=(AT91_MC_FMR_1FWS)
- str r1,[r0,#AT91_MC_FMR]
-#endif
#if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 60000000
ldr r1,=(AT91_MC_FMR_2FWS)
+#else
+ ldr r1,=(AT91_MC_FMR_1FWS)
+#endif
str r1,[r0,#AT91_MC_FMR]
#endif
.endm
@@ -79,7 +79,11 @@
ldr r1,=(AT91_PMC_MCKR_PRES_CLK|AT91_PMC_MCKR_SLOW_CLK)
str r1,[r0,#AT91_PMC_MCKR]
// startup time
+#if defined(CYGNUM_HAL_ARM_AT91_CLOCK_TYPE_EXTCLOCK)
+ ldr r1,=(AT91_PMC_MOR_OSCBYPASS)
+#else
ldr r1,=(AT91_PMC_MOR_OSCCOUNT(6)|AT91_PMC_MOR_MOSCEN)
+#endif
str r1,[r0,#AT91_PMC_MOR]
// Wait for oscilator start timeout