? hal/arm/at91/at91sam7sek ? hal/arm/at91/at91sam7xek Index: NEWS =================================================================== RCS file: /cvs/ecos/ecos/packages/NEWS,v retrieving revision 1.100 diff -u -r1.100 NEWS --- NEWS 31 May 2006 19:15:37 -0000 1.100 +++ NEWS 2 Jun 2006 18:10:51 -0000 @@ -1,3 +1,4 @@ +* Port to ATMEL AT91SAM7X by John Eigelaar * Freescale MAC7100 varient and SIva MACE1 platfrom by Ilija Koco. * Coldfire architecture HAL, the mcf5272 varient HAL and the m5272c3 platform HAL. Contributed by Enrico Piria. Index: ecos.db =================================================================== RCS file: /cvs/ecos/ecos/packages/ecos.db,v retrieving revision 1.151 diff -u -r1.151 ecos.db --- ecos.db 31 May 2006 19:15:38 -0000 1.151 +++ ecos.db 2 Jun 2006 18:10:59 -0000 @@ -2533,14 +2533,34 @@ the Atmel evaluation board AT572D74-DK1." } -package CYGPKG_HAL_ARM_AT91SAM7S { - alias { "Atmel AT91SAM7S" hal_arm_at91sam7s arm_at91_sam7s } +package CYGPKG_HAL_ARM_AT91SAM7 { + alias { "Atmel AT91SAM7" hal_arm_at91sam7 arm_at91_sam7 } directory hal/arm/at91/at91sam7s script hal_arm_at91sam7s.cdl hardware description " - The at91sam7s HAL package provides the support needed to run eCos on - an Atmel evaluation board for the AT91SAM7S." + The at91sam7 HAL package provides the support needed to run eCos on + an Atmel AT91SAM7 family of CPUs." +} + +package CYGPKG_HAL_ARM_AT91SAM7SEK { + alias { "Atmel AT91SAM7S" hal_arm_at91sam7sek arm_at91_sam7sek } + directory hal/arm/at91/at91sam7sek + script hal_arm_at91sam7sek.cdl + hardware + description " + The at91sam7sek HAL package provides the support needed to run eCos on + an Atmel AT91SAM7S-EK development board." +} + +package CYGPKG_HAL_ARM_AT91SAM7XEK { + alias { "Atmel AT91SAM7X" hal_arm_at91sam7xek arm_at91_sam7xek } + directory hal/arm/at91/at91sam7xek + script hal_arm_at91sam7xek.cdl + hardware + description " + The at91sam7xek HAL package provides the support needed to run eCos on + an Atmel AT91SAM7X-EK development board." } package CYGPKG_HAL_ARM_AT91_EB40 { @@ -4291,11 +4311,29 @@ Diospsis evaluation board (jtst)." } -target at91sam7s { - alias { "Atmel AT91SAM7S evaluation board" at91_at91sam7s } +target at91sam7sek { + alias { "Atmel AT91SAM7SEK evaluation board" at91_at91sam7sek } + packages { CYGPKG_HAL_ARM + CYGPKG_HAL_ARM_AT91 + CYGPKG_HAL_ARM_AT91SAM7 + CYGPKG_HAL_ARM_AT91SAM7SEK + CYGPKG_IO_SERIAL_ARM_AT91 + CYGPKG_DEVS_FLASH_AT91 + CYGPKG_DEVS_SPI_ARM_AT91 + CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC + CYGPKG_DEVS_USB_AT91 + } + description " + The at91sam7sek target provides the packages needed to run eCos on an + Atmel AT91SAM7S-EK evaluation board." +} + +target at91sam7xek { + alias { "Atmel AT91SAM7XEK evaluation board" at91_at91sam7xek } packages { CYGPKG_HAL_ARM CYGPKG_HAL_ARM_AT91 - CYGPKG_HAL_ARM_AT91SAM7S + CYGPKG_HAL_ARM_AT91SAM7 + CYGPKG_HAL_ARM_AT91SAM7XEK CYGPKG_IO_SERIAL_ARM_AT91 CYGPKG_DEVS_FLASH_AT91 CYGPKG_DEVS_SPI_ARM_AT91 Index: ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/ChangeLog,v retrieving revision 1.164 diff -u -r1.164 ChangeLog --- ChangeLog 31 May 2006 19:15:37 -0000 1.164 +++ ChangeLog 2 Jun 2006 18:11:02 -0000 @@ -1,3 +1,7 @@ +2006-06-02 Andrew Lunn + + * ecos.db: Add AT91SAM7SEK and AT91SAM7XEK packages and targets + 2006-05-24 Ilija Koco * ecos.db: Add Freescale MAC7100 variant, SIvA MACE1 platform Index: hal/arm/at91/at91sam7s/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/ChangeLog,v retrieving revision 1.6 diff -u -r1.6 ChangeLog --- hal/arm/at91/at91sam7s/current/ChangeLog 8 Apr 2006 14:53:43 -0000 1.6 +++ hal/arm/at91/at91sam7s/current/ChangeLog 2 Jun 2006 18:11:02 -0000 @@ -1,3 +1,24 @@ +2006-06-01 Andrew Lunn + + * cdl/hal_arm_at91sam7s.cdl: Implement the SPI bus 1 interface for + the SAM7X and SAM7XC. + +2006-06-01 John Eigelaar + + * include/plf_io.h: Add SPI DMA registers. + +2006-05-20 John Eigelaar + + include/pkgconf/mlt_arm_at91sam7x128_rom.{h|ldi} + include/pkgconf/mlt_arm_at91sam7x256_rom.{h|ldi}: Linker files + for AT91SAM7X processor. + +2006-05-17 Andrew Lunn + + * src/at91sam7s_misc.c: Use the AT91 generic PIO manipulation + macros. Move the LED function out into the board specific HAL + package. + 2006-04-07 Andrew Lunn * cdl/hal_arm_at91sam7s.cdl: Index: hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl,v retrieving revision 1.4 diff -u -r1.4 hal_arm_at91sam7s.cdl --- hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl 8 Apr 2006 14:53:43 -0000 1.4 +++ hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl 2 Jun 2006 18:11:02 -0000 @@ -2,7 +2,7 @@ # # hal_arm_at91_sam7s.cdl # -# ARM AT91 SAM7S HAL package configuration data +# ARM AT91 SAM7 HAL package configuration data # # ==================================================================== #####ECOSGPLCOPYRIGHTBEGIN#### @@ -46,21 +46,20 @@ # # ==================================================================== -cdl_package CYGPKG_HAL_ARM_AT91SAM7S { - display "Atmel AT91SAM7S HAL" +cdl_package CYGPKG_HAL_ARM_AT91SAM7 { + display "Atmel AT91SAM7 HAL" parent CYGPKG_HAL_ARM - define_header hal_arm_at91sam7s.h + define_header hal_arm_at91sam7.h include_dir cyg/hal hardware description " - The AT91SAM7S HAL package provides the support needed to run - eCos on an Atmel AT91SAM7S based board." + The AT91SAM7 HAL package provides the support needed to run + eCos on an Atmel AT91SAM7 based board." compile at91sam7s_misc.c - requires { CYGHWR_HAL_ARM_AT91 == "AT91SAM7S" } requires { CYGHWR_HAL_ARM_AT91_FIQ } - requires { CYGHWR_HAL_ARM_AT91SAM7S == "at91sam7s32" implies + requires { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s32" implies CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0 == 0 } implements CYGINT_HAL_ARM_AT91_SERIAL_DBG_HW @@ -70,29 +69,60 @@ define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H " puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H " - puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H" puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM7TDMI\"" - puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Atmel (at91sam7s)\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Atmel (at91sam7)\"" puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" } - cdl_option CYGHWR_HAL_ARM_AT91SAM7S { - display "AT91SAM7S variant used" + cdl_option CYGHWR_HAL_ARM_AT91SAM7 { + display "AT91SAM7 variant used" flavor data default_value {"at91sam7s256"} legal_values {"at91sam7s32" "at91sam7s321" "at91sam7s64" - "at91sam7s128" "at91sam7s256"} + "at91sam7s128" "at91sam7s256" + "at91sam7x128" "at91sam7x256" + "at91sam7xc128" "at91sam7xc256" } description " - The AT91SAM7S microcontroller family has several variants, + The AT91SAM7 microcontroller family has several variants, the main differences being the amount of on-chip SRAM, FLASH, peripherals and their layout. This option allows the platform HALs to select the specific microcontroller being used." } - cdl_option CYGBLD_HAL_ARM_AT91SAM7S_USB { - active_if {!( "at91sam7s32" == CYGHWR_HAL_ARM_AT91SAM7S) } + cdl_option CYGHWR_HAL_ARM_AT91SAM7S { + display "SAM7S device" + calculated { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s256" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s128" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s64" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s32" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s321" } + description " + Is the AT91SAM7 device a member of the AT91SAM7S family?" + } + + cdl_option CYGHWR_HAL_ARM_AT91SAM7X { + display "SAM7X device" + calculated { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x256" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x128" } + description " + Is the AT91SAM7 device a member of the AT91SAM7X family?" + } + + cdl_option CYGHWR_HAL_ARM_AT91SAM7XC { + display "SAM7XC device" + calculated { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7xc256" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7xc128" } + description " + Is the AT91SAM7 device a member of the AT91SAM7XC family?" + } + + cdl_option CYGBLD_HAL_ARM_AT91SAM7_USB { + active_if {!( "at91sam7s32" == CYGHWR_HAL_ARM_AT91SAM7S) || + CYGHWR_HAL_ARM_AT91SAM7X || + CYGHWR_HAL_ARM_AT91SAM7XC } implements CYGINT_DEVS_USB_AT91_HAS_USB default_value 1 no_define @@ -100,6 +130,16 @@ All but the AT91SAM7S32 has the USB device" } + cdl_option CYGBLD_HAL_ARM_AT91SAM7_SPI1 { + active_if { CYGHWR_HAL_ARM_AT91SAM7X || + CYGHWR_HAL_ARM_AT91SAM7XC } + implements CYGINT_DEVS_SPI_ARM_AT91_HAS_BUS1 + default_value 1 + no_define + description " + The SAM7X and SAM7XC have the second SPI bus controller" + } + cdl_component CYGNUM_HAL_RTC_CONSTANTS { display "Real-time clock constants" flavor none @@ -132,7 +172,7 @@ no_define define -file system.h CYG_HAL_STARTUP description " - When targeting the AT91SAM7S eval board it is possible to build + When targeting the AT91SAM7 eval boards it is possible to build the system for either RAM bootstrap or ROM bootstrap(s). Select 'ram' when building programs to load into RAM using on board debug software such as Angel or eCos GDB stubs. Select 'rom' @@ -379,8 +419,8 @@ flavor data no_define calculated { (CYG_HAL_STARTUP == "RAM") ? \ - "arm_" . CYGHWR_HAL_ARM_AT91SAM7S . "_ram" : - "arm_" . CYGHWR_HAL_ARM_AT91SAM7S . "_rom" } + "arm_" . CYGHWR_HAL_ARM_AT91SAM7 . "_ram" : + "arm_" . CYGHWR_HAL_ARM_AT91SAM7 . "_rom" } cdl_option CYGHWR_MEMORY_LAYOUT_LDI { display "Memory layout linker script fragment" @@ -388,8 +428,8 @@ no_define define -file system.h CYGHWR_MEMORY_LAYOUT_LDI calculated { (CYG_HAL_STARTUP == "RAM") ? \ - "" : - "" } + "" : + "" } } cdl_option CYGHWR_MEMORY_LAYOUT_H { @@ -398,8 +438,8 @@ no_define define -file system.h CYGHWR_MEMORY_LAYOUT_H calculated { (CYG_HAL_STARTUP == "RAM") ? \ - "" : - "" } + "" : + "" } } } } Index: hal/arm/at91/at91sam7s/current/include/hal_platform_ints.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/hal_platform_ints.h,v retrieving revision 1.1 diff -u -r1.1 hal_platform_ints.h --- hal/arm/at91/at91sam7s/current/include/hal_platform_ints.h 19 Feb 2006 20:32:24 -0000 1.1 +++ hal/arm/at91/at91sam7s/current/include/hal_platform_ints.h 2 Jun 2006 18:11:03 -0000 @@ -4,7 +4,7 @@ // // hal_platform_ints.h // -// HAL Interrupt and clock assignments for AT91SAM7S +// HAL Interrupt and clock assignments for AT91SAM7 // //========================================================================== //####ECOSGPLCOPYRIGHTBEGIN#### @@ -41,10 +41,10 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): gthomas -// Contributors: gthomas, Oliver Munz, Andrew Lunn +// Contributors: gthomas, Oliver Munz, Andrew Lunn, John Eigelaar // Date: 2001-07-12 // Purpose: Define Interrupt support -// Description: The interrupt specifics for the AT91SAM7Splatform are +// Description: The interrupt specifics for the AT91SAM7 platform are // defined here. // // Usage: #include @@ -55,13 +55,23 @@ // //========================================================================== +#include + #define CYGNUM_HAL_INTERRUPT_FIQ 0 #define CYGNUM_HAL_INTERRUPT_SYS 1 #define CYGNUM_HAL_INTERRUPT_PIOA 2 +#ifdef CYGHWR_HAL_ARM_AT91SAM7X +#define CYGNUM_HAL_INTERRUPT_PIOB 3 +#define CYGNUM_HAL_INTERRUPT_SPI 4 +#define CYGNUM_HAL_INTERRUPT_SPI1 5 +#endif +#ifdef CYGHWR_HAL_ARM_AT91SAM7S #define CYGNUM_HAL_INTERRUPT_ADC 4 #define CYGNUM_HAL_INTERRUPT_SPI 5 +#endif + #define CYGNUM_HAL_INTERRUPT_USART0 6 #define CYGNUM_HAL_INTERRUPT_USART1 7 #define CYGNUM_HAL_INTERRUPT_SSC 8 @@ -72,6 +82,12 @@ #define CYGNUM_HAL_INTERRUPT_TC1 13 #define CYGNUM_HAL_INTERRUPT_TC2 14 +#ifdef CYGHWR_HAL_ARM_AT91SAM7X +#define CYGNUM_HAL_INTERRUPT_CAN 15 +#define CYGNUM_HAL_INTERRUPT_EMAC 16 +#define CYGNUM_HAL_INTERRUPT_ADC 17 +#endif + #define CYGNUM_HAL_INTERRUPT_IRQ0 30 #define CYGNUM_HAL_INTERRUPT_IRQ1 31 Index: hal/arm/at91/at91sam7s/current/include/plf_io.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/plf_io.h,v retrieving revision 1.3 diff -u -r1.3 plf_io.h --- hal/arm/at91/at91sam7s/current/include/plf_io.h 13 Mar 2006 07:48:20 -0000 1.3 +++ hal/arm/at91/at91sam7s/current/include/plf_io.h 2 Jun 2006 18:11:03 -0000 @@ -49,12 +49,36 @@ //####DESCRIPTIONEND#### // //============================================================================= +#include #define CYGARC_PHYSICAL_ADDRESS(_x_) +//SPI - Serial Peripheral Interface #define AT91_SPI0 0xFFFE0000 -#define AT91_PIOA 0xfffff400 +#ifdef CYGHWR_HAL_ARM_AT91SAM7X +#define AT91_SPI1 0xFFFE4000 +#endif + +#define AT91_SPI AT91_SPI0 + +// DMA registers +#define AT91_SPI_RPR 0x100 // Receive Pointer Register +#define AT91_SPI_RCR 0x104 // Receive Counter Register +#define AT91_SPI_TPR 0x108 // Transmit Pointer Register +#define AT91_SPI_TCR 0x10C // Transmit Counter Register +#define AT91_SPI_NRPR 0x110 // Next Receive Pointer Register +#define AT91_SPI_NRCR 0x114 // Next Receive Counter Register +#define AT91_SPI_NTPR 0x118 // Next Transmit Pointer Register +#define AT91_SPI_NTCR 0x11C // Next Trsnsmit Counter Register +#define AT91_SPI_PTCR 0x120 // PDC Transfer Control Register +#define AT91_SPI_PTSR 0x124 // PDC Transfer Status Register + +// Peripheral Input/Output Controllers +#define AT91_PIOA 0xFFFFF400 +#ifdef CYGHWR_HAL_ARM_AT91SAM7X +#define AT91_PIOB 0xFFFFF600 +#endif #define AT91_WSTC 0xFFFFFD40 @@ -89,7 +113,7 @@ // PIO - Programmable I/O -#define AT91_PIO 0xFFFFF400 +#define AT91_PIO AT91_PIOA // AIC - Advanced Interrupt Controller @@ -145,6 +169,18 @@ #define AT91_PMC_SR_PCK3RDY (1 << 11) // Pad clock 3 is ready to be enabled #define AT91_PMC_IMR 0x6c // Interrupt Mask Register +#ifdef CYGHWR_HAL_ARM_AT91SAM7X + +// EMAC - Ethernet Medium Access Controller + +#define AT91_EMAC 0xFFFDC000 + +// CAN - Controller Area Network + +#define AT91_CAN 0xFFFD0000 + +#endif + //---------------------------------------------------------------------- // The platform needs this initialization during the // hal_hardware_init() function in the varient HAL. Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s128_rom.ldi =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s128_rom.ldi,v retrieving revision 1.2 diff -u -r1.2 mlt_arm_at91sam7s128_rom.ldi --- hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s128_rom.ldi 8 Apr 2006 14:53:43 -0000 1.2 +++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s128_rom.ldi 2 Jun 2006 18:11:03 -0000 @@ -3,7 +3,7 @@ // This is a generated file - do not edit #include -#include +#include MEMORY { Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s256_rom.ldi =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s256_rom.ldi,v retrieving revision 1.2 diff -u -r1.2 mlt_arm_at91sam7s256_rom.ldi --- hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s256_rom.ldi 8 Apr 2006 14:53:43 -0000 1.2 +++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s256_rom.ldi 2 Jun 2006 18:11:03 -0000 @@ -3,7 +3,7 @@ // This is a generated file - do not edit #include -#include +#include MEMORY { Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s32_rom.ldi =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s32_rom.ldi,v retrieving revision 1.2 diff -u -r1.2 mlt_arm_at91sam7s32_rom.ldi --- hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s32_rom.ldi 8 Apr 2006 14:53:43 -0000 1.2 +++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s32_rom.ldi 2 Jun 2006 18:11:03 -0000 @@ -3,7 +3,7 @@ // This is a generated file - do not edit #include -#include +#include MEMORY { Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s64_rom.ldi =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s64_rom.ldi,v retrieving revision 1.2 diff -u -r1.2 mlt_arm_at91sam7s64_rom.ldi --- hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s64_rom.ldi 8 Apr 2006 14:53:43 -0000 1.2 +++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s64_rom.ldi 2 Jun 2006 18:11:03 -0000 @@ -3,7 +3,7 @@ // This is a generated file - do not edit #include -#include +#include MEMORY { Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x128_rom.h =================================================================== RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x128_rom.h diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x128_rom.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x128_rom.h 2 Jun 2006 18:11:03 -0000 @@ -0,0 +1,25 @@ +// eCos memory layout - Wed Apr 11 13:49:55 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include +#include + +#endif +#define CYGMEM_REGION_ram (0x00200000) +#define CYGMEM_REGION_ram_SIZE (0x08000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x00100000) +#define CYGMEM_REGION_rom_SIZE (0x20000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_bootmon) []; +#endif +#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon)) +#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x01000) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x00204000 - (size_t) CYG_LABEL_NAME (__heap1)) Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x128_rom.ldi =================================================================== RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x128_rom.ldi diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x128_rom.ldi --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x128_rom.ldi 2 Jun 2006 18:11:03 -0000 @@ -0,0 +1,30 @@ +// eCos memory layout - Wed Apr 11 13:49:55 2001 + +// This is a generated file - do not edit + +#include +#include + +MEMORY +{ + ram : ORIGIN = 0x00200000, LENGTH = 0x08000 + rom : ORIGIN = 0x00100000, LENGTH = 0x20000 +} + +SECTIONS +{ + SECTIONS_BEGIN + CYG_LABEL_DEFN(__reserved_bootmon) = 0x00000000; . = CYG_LABEL_DEFN(__reserved_bootmon) + 0x01000; + SECTION_rom_vectors (rom, CYGNUM_HAL_ARM_AT91_IMAGE_ADDRESS, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x00200040, LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x256_rom.h =================================================================== RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x256_rom.h diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x256_rom.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x256_rom.h 2 Jun 2006 18:11:03 -0000 @@ -0,0 +1,25 @@ +// eCos memory layout - Wed Apr 11 13:49:55 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include +#include + +#endif +#define CYGMEM_REGION_ram (0x00200000) +#define CYGMEM_REGION_ram_SIZE (0x10000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x00100000) +#define CYGMEM_REGION_rom_SIZE (0x40000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_bootmon) []; +#endif +#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon)) +#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x01000) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x00210000 - (size_t) CYG_LABEL_NAME (__heap1)) Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x256_rom.ldi =================================================================== RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x256_rom.ldi diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x256_rom.ldi --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7x256_rom.ldi 2 Jun 2006 18:11:03 -0000 @@ -0,0 +1,30 @@ +// eCos memory layout - Wed Apr 11 13:49:55 2001 + +// This is a generated file - do not edit + +#include +#include + +MEMORY +{ + ram : ORIGIN = 0x00200000, LENGTH = 0x10000 + rom : ORIGIN = 0x00100000, LENGTH = 0x40000 +} + +SECTIONS +{ + SECTIONS_BEGIN + CYG_LABEL_DEFN(__reserved_bootmon) = 0x00000000; . = CYG_LABEL_DEFN(__reserved_bootmon) + 0x01000; + SECTION_rom_vectors (rom, CYGNUM_HAL_ARM_AT91_IMAGE_ADDRESS, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x00200040, LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} Index: hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c,v retrieving revision 1.3 diff -u -r1.3 at91sam7s_misc.c --- hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c 13 Mar 2006 07:48:20 -0000 1.3 +++ hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c 2 Jun 2006 18:11:04 -0000 @@ -68,18 +68,7 @@ #include // HAL ISR support #endif -// The development board has four LEDs -void -hal_at91_led (int val) -{ - HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_PPUDR, 0x0000000f); // Disable pull ups - HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_OER, 0x0000000f); // Enable Output - HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_PER, 0x0000000f); // Enable Output - HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_ASR, 0x0000000f); - - HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, 0x0000000f); // All off - HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, (val & 0xf)); -} +extern void hal_at91_led(int val); void hal_at91_set_leds (int val) @@ -93,22 +82,15 @@ void hal_plf_hardware_init (void) { /* Enable the Serial devices to driver the serial port pins */ - HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_PDR, - AT91_PIO_PSR_RXD0 | AT91_PIO_PSR_TXD0 | AT91_PIO_PSR_DTXD); - - /* Set the serial port pins to PIOA */ - HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_ASR, - AT91_PIO_PSR_RXD0 | AT91_PIO_PSR_TXD0 | - AT91_PIO_PSR_DRXD | AT91_PIO_PSR_DTXD); + HAL_ARM_AT91_PIO_CFG(AT91_USART_RXD0); + HAL_ARM_AT91_PIO_CFG(AT91_USART_TXD0); + HAL_ARM_AT91_PIO_CFG(AT91_DBG_DTXD); + HAL_ARM_AT91_PIO_CFG(AT91_DBG_DRXD); #if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32) /* Enable the Serial devices to driver the serial port pins */ - HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_PDR, - AT91_PIO_PSR_RXD1 | AT91_PIO_PSR_TXD1); - - /* Set the serial port pins to PIOA */ - HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_ASR, - AT91_PIO_PSR_RXD1 | AT91_PIO_PSR_TXD1); + HAL_ARM_AT91_PIO_CFG(AT91_USART_RXD1); + HAL_ARM_AT91_PIO_CFG(AT91_USART_TXD1); #endif /* Setup the Reset controller. Allow user resets */ Index: hal/arm/at91/var/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/ChangeLog,v retrieving revision 1.35 diff -u -r1.35 ChangeLog --- hal/arm/at91/var/current/ChangeLog 26 Apr 2006 13:26:20 -0000 1.35 +++ hal/arm/at91/var/current/ChangeLog 2 Jun 2006 18:11:05 -0000 @@ -1,3 +1,27 @@ +2006-06-01 John Eigelaar + + * include/var_io.h: Added SPI PDC register definitions + +2006-05-20 John Eigelaar + + * include/var_io.h: AT91SAM7X pin definitions + * include/hal_platform_int.h: AT91SAM7X interrupts + * include/plf_io.h: AT91SAM7X device addresses. + +2006-05-20 Andrew Lunn + + * cdl/hal_arm_at91sam7s.cdl: Rename to AT91SAM7 and add support + for AT91SAM7X, based on code from John Eigelaar. + * include/var_io.h: add CAN, TWI and ADC registers. + +2006-05-17 Andrew Lunn + + * include/var_io.h: Add macros to manipulate the PIO controllers. + +2006-05-10 Andrew Lunn + + * include/var_io.h: Added the Ethernet MAC registers. + 2006-04-26 John Eigelaar * include/var_io.h: Fix typo's in the USB register definitions Index: hal/arm/at91/var/current/include/var_arch.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_arch.h,v retrieving revision 1.3 diff -u -r1.3 var_arch.h --- hal/arm/at91/var/current/include/var_arch.h 19 Feb 2006 19:08:28 -0000 1.3 +++ hal/arm/at91/var/current/include/var_arch.h 2 Jun 2006 18:11:05 -0000 @@ -75,7 +75,7 @@ #elif defined(CYGHWR_HAL_ARM_AT91_M42800A) || \ defined(CYGHWR_HAL_ARM_AT91_M55800A) || \ - defined(CYGHWR_HAL_ARM_AT91SAM7S) + defined(CYGHWR_HAL_ARM_AT91SAM7) #define HAL_IDLE_THREAD_ACTION(_count_) \ CYG_MACRO_START \ Index: hal/arm/at91/var/current/include/var_io.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h,v retrieving revision 1.16 diff -u -r1.16 var_io.h --- hal/arm/at91/var/current/include/var_io.h 26 Apr 2006 13:26:20 -0000 1.16 +++ hal/arm/at91/var/current/include/var_io.h 2 Jun 2006 18:11:10 -0000 @@ -42,7 +42,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): jskov -// Contributors:jskov, gthomas, tkoeller, tdrury, nickg, asl +// Contributors:jskov, gthomas, tkoeller, tdrury, nickg, asl, John Eigelaar // Date: 2001-07-12 // Purpose: AT91 variant specific registers // Description: @@ -167,12 +167,131 @@ #define AT91_PIO 0xFFFF0000 #endif +#define AT91_PIN(_ctrl_, _periph_, _pin_) \ + ((_ctrl_ << 16) | (_periph_ << 8) | (_pin_)) + #define AT91_PIO_PER 0x00 // PIO enable #define AT91_PIO_PDR 0x04 // PIO disable #define AT91_PIO_PSR 0x08 // PIO status +// GPIO pins on PIO A. +#define AT91_GPIO_PA0 AT91_PIN(0,0, 0) +#define AT91_GPIO_PA1 AT91_PIN(0,0, 1) +#define AT91_GPIO_PA2 AT91_PIN(0,0, 2) +#define AT91_GPIO_PA3 AT91_PIN(0,0, 3) +#define AT91_GPIO_PA4 AT91_PIN(0,0, 4) +#define AT91_GPIO_PA5 AT91_PIN(0,0, 5) +#define AT91_GPIO_PA6 AT91_PIN(0,0, 6) +#define AT91_GPIO_PA7 AT91_PIN(0,0, 7) +#define AT91_GPIO_PA8 AT91_PIN(0,0, 8) +#define AT91_GPIO_PA9 AT91_PIN(0,0, 9) +#define AT91_GPIO_PA10 AT91_PIN(0,0,10) +#define AT91_GPIO_PA11 AT91_PIN(0,0,11) +#define AT91_GPIO_PA12 AT91_PIN(0,0,12) +#define AT91_GPIO_PA13 AT91_PIN(0,0,13) +#define AT91_GPIO_PA14 AT91_PIN(0,0,14) +#define AT91_GPIO_PA15 AT91_PIN(0,0,15) +#define AT91_GPIO_PA16 AT91_PIN(0,0,16) +#define AT91_GPIO_PA17 AT91_PIN(0,0,17) +#define AT91_GPIO_PA18 AT91_PIN(0,0,18) +#define AT91_GPIO_PA19 AT91_PIN(0,0,19) +#define AT91_GPIO_PA20 AT91_PIN(0,0,20) +#define AT91_GPIO_PA21 AT91_PIN(0,0,21) +#define AT91_GPIO_PA22 AT91_PIN(0,0,22) +#define AT91_GPIO_PA23 AT91_PIN(0,0,23) +#define AT91_GPIO_PA24 AT91_PIN(0,0,24) +#define AT91_GPIO_PA25 AT91_PIN(0,0,25) +#define AT91_GPIO_PA26 AT91_PIN(0,0,26) +#define AT91_GPIO_PA27 AT91_PIN(0,0,27) +#define AT91_GPIO_PA28 AT91_PIN(0,0,28) +#define AT91_GPIO_PA29 AT91_PIN(0,0,29) +#define AT91_GPIO_PA30 AT91_PIN(0,0,30) +#define AT91_GPIO_PA31 AT91_PIN(0,0,31) + +#ifdef AT91_PIOB +// GPIO pins on PIOB. +#define AT91_GPIO_PB0 AT91_PIN(1,0, 0) +#define AT91_GPIO_PB1 AT91_PIN(1,0, 1) +#define AT91_GPIO_PB2 AT91_PIN(1,0, 2) +#define AT91_GPIO_PB3 AT91_PIN(1,0, 3) +#define AT91_GPIO_PB4 AT91_PIN(1,0, 4) +#define AT91_GPIO_PB5 AT91_PIN(1,0, 5) +#define AT91_GPIO_PB6 AT91_PIN(1,0, 6) +#define AT91_GPIO_PB7 AT91_PIN(1,0, 7) +#define AT91_GPIO_PB8 AT91_PIN(1,0, 8) +#define AT91_GPIO_PB9 AT91_PIN(1,0, 9) +#define AT91_GPIO_PB10 AT91_PIN(1,0,10) +#define AT91_GPIO_PB11 AT91_PIN(1,0,11) +#define AT91_GPIO_PB12 AT91_PIN(1,0,12) +#define AT91_GPIO_PB13 AT91_PIN(1,0,13) +#define AT91_GPIO_PB14 AT91_PIN(1,0,14) +#define AT91_GPIO_PB15 AT91_PIN(1,0,15) +#define AT91_GPIO_PB16 AT91_PIN(1,0,16) +#define AT91_GPIO_PB17 AT91_PIN(1,0,17) +#define AT91_GPIO_PB18 AT91_PIN(1,0,18) +#define AT91_GPIO_PB19 AT91_PIN(1,0,19) +#define AT91_GPIO_PB20 AT91_PIN(1,0,20) +#define AT91_GPIO_PB21 AT91_PIN(1,0,21) +#define AT91_GPIO_PB22 AT91_PIN(1,0,22) +#define AT91_GPIO_PB23 AT91_PIN(1,0,23) +#define AT91_GPIO_PB24 AT91_PIN(1,0,24) +#define AT91_GPIO_PB25 AT91_PIN(1,0,25) +#define AT91_GPIO_PB26 AT91_PIN(1,0,26) +#define AT91_GPIO_PB27 AT91_PIN(1,0,27) +#define AT91_GPIO_PB28 AT91_PIN(1,0,28) +#define AT91_GPIO_PB29 AT91_PIN(1,0,29) +#define AT91_GPIO_PB30 AT91_PIN(1,0,30) +#define AT91_GPIO_PB31 AT91_PIN(1,0,31) +#endif //AT91_PIOB + #if defined(CYGHWR_HAL_ARM_AT91_M55800A) +#define AT91_TC_TCLK3 AT91_PIN(0,0, 0) // Timer 3 Clock signal +#define AT91_TC_TIOA3 AT91_PIN(0,0, 1) // Timer 3 Signal A +#define AT91_TC_TIOB3 AT91_PIN(0,0, 2) // Timer 3 Signal B +#define AT91_TC_TCLK4 AT91_PIN(0,0, 3) // Timer 4 Clock signal +#define AT91_TC_TIOA4 AT91_PIN(0,0, 4) // Timer 4 Signal A +#define AT91_TC_TIOB4 AT91_PIN(0,0, 5) // Timer 4 Signal B +#define AT91_TC_TCLK5 AT91_PIN(0,0, 6) // Timer 5 Clock signal +#define AT91_TC_TIOA5 AT91_PIN(0,0, 7) // Timer 5 Signal A +#define AT91_TC_TIOB5 AT91_PIN(0,0, 8) // Timer 5 Signal B +#define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // External Interrupt 0 +#define AT91_INT_IRQ1 AT91_PIN(0,0,10) // External Interrupt 1 +#define AT91_INT_IRQ2 AT91_PIN(0,0,11) // External Interrupt 2 +#define AT91_INT_IRQ3 AT91_PIN(0,0,12) // External Interrupt 3 +#define AT91_INT_FIQ AT91_PIN(0,0,13) // Fast Interrupt +#define AT91_USART_SCK0 AT91_PIN(0,0,14) // USART 0 Clock signal +#define AT91_USART_TXD0 AT91_PIN(0,0,15) // USART 0 transmit data +#define AT91_USART_RXD0 AT91_PIN(0,0,16) // USART 0 receive data +#define AT91_USART_SCK1 AT91_PIN(0,0,17) // USART 1 Clock signal +#define AT91_USART_TXD1 AT91_PIN(0,0,18) // USART 1 transmit data +#define AT91_USART_RXD1 AT91_PIN(0,0,19) // USART 1 receive data +#define AT91_USART_SCK2 AT91_PIN(0,0,20) // USART 2 Clock signal +#define AT91_USART_TXD2 AT91_PIN(0,0,21) // USART 2 transmit data +#define AT91_USART_RXD2 AT91_PIN(0,0,22) // USART 2 receive data +#define AT91_SPI_SPCK AT91_PIN(0,0,23) // SPI Clock signal +#define AT91_SPI_MISO AT91_PIN(0,0,24) // SPI Master In Slave Out +#define AT91_SPI_MOIS AT91_PIN(0,0,25) // SPI Master Out Slave In +#define AT91_SPI_NPCS0 AT91_PIN(0,0,26) // SPI Peripheral Chip Select 0 +#define AT91_SPI_NPCS1 AT91_PIN(0,0,27) // SPI Peripheral Chip Select 1 +#define AT91_SPI_NPCS2 AT91_PIN(0,0,28) // SPI Peripheral Chip Select 2 +#define AT91_SPI_NPCS3 AT91_PIN(0,0,29) // SPI Peripheral Chip Select 3 + +#define AT91_INT_IRQ4 AT91_PIN(1,0, 3) // External Interrupt 4 +#define AT91_INT_IRQ5 AT91_PIN(1,0, 4) // External Interrupt 5 +#define AT91_ADC_AD0TRIG AT91_PIN(1,0, 6) // ADC0 External Trigger +#define AT91_ADC_AD1TRIG AT91_PIN(1,0, 7) // ADC1 External Trigger +#define AT91_BOOT_BMS AT91_PIN(1,0,12) // Boot Mode Select +#define AT91_TC_TCLK0 AT91_PIN(1,0,14) // Timer 0 Clock signal +#define AT91_TC_TIOA0 AT91_PIN(1,0,15) // Timer 0 Signal A +#define AT91_TC_TIOB0 AT91_PIN(1,0,16) // Timer 0 Signal B +#define AT91_TC_TCLK1 AT91_PIN(1,0,17) // Timer 1 Clock signal +#define AT91_TC_TIOA1 AT91_PIN(1,0,18) // Timer 1 Signal A +#define AT91_TC_TIOB1 AT91_PIN(1,0,19) // Timer 1 Signal B +#define AT91_TC_TCLK2 AT91_PIN(1,0,20) // Timer 2 Clock signal +#define AT91_TC_TIOA2 AT91_PIN(1,0,21) // Timer 2 Signal A +#define AT91_TC_TIOB2 AT91_PIN(1,0,22) // Timer 2 Signal B + // PIOA #define AT91_PIO_PSR_TCLK3 0x00000001 // Timer 3 Clock signal #define AT91_PIO_PSR_TIOA3 0x00000002 // Timer 3 Signal A @@ -221,10 +340,81 @@ #define AT91_PIO_PSR_TIOA2 0x04000000 // Timer 2 Signal A #define AT91_PIO_PSR_TIOB2 0x08000000 // Timer 2 Signal B -#elif defined (CYGHWR_HAL_ARM_AT91SAM7S) -#include +#elif defined (CYGHWR_HAL_ARM_AT91SAM7) +#include -// PIOA +#ifdef CYGHWR_HAL_ARM_AT91SAM7S +#define AT91_PWM_PWM0 AT91_PIN(0,0, 0) // Pulse Width Modulation 0 +#define AT91_PWM_PWM1 AT91_PIN(0,0, 1) // Pulse Width Modulation 1 +#define AT91_PWM_PWM2 AT91_PIN(0,0, 2) // Pulse Width Modulation 2 +#define AT91_TWI_TWD AT91_PIN(0,0, 3) // Two Wire Data +#define AT91_TWI_TWCK AT91_PIN(0,0, 4) // Two Wire Clock +#define AT91_USART_RXD0 AT91_PIN(0,0, 5) // USART 0 Receive Data +#define AT91_USART_TXD0 AT91_PIN(0,0, 6) // USART 0 Transmit Data +#define AT91_USART_RTS0 AT91_PIN(0,0, 7) // USART 0 Ready To Send +#define AT91_USART_CTS0 AT91_PIN(0,0, 8) // USART 0 Clear To Send +#define AT91_DBG_DRXD AT91_PIN(0,0, 9) // Debug UART Receive +#define AT91_DBG_DTXD AT91_PIN(0,0,10) // Debug UART Transmit +#define AT91_SPI_NPCS0 AT91_PIN(0,0,11) // SPI Chip Select 0 +#define AT91_SPI_MISO AT91_PIN(0,0,12) // SPI Input +#define AT91_SPI_MOIS AT91_PIN(0,0,13) // SPI Output +#define AT91_SPI_SPCK AT91_PIN(0,0,14) // SPI clock +#define AT91_S2C_TF AT91_PIN(0,0,15) // S2C Transmit Frame Sync +#define AT91_S2C_TK AT91_PIN(0,0,16) // S2C Transmit Clock +#define AT91_S2C_TD AT91_PIN(0,0,17) // S2C Transmit Data +#define AT91_S2C_RD AT91_PIN(0,0,18) // S2C Receive Data +#define AT91_S2C_RK AT91_PIN(0,0,19) // S2C Receive Clock +#define AT91_S2C_RF AT91_PIN(0,0,20) // S2C Receive Frame Sync +#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32) +#define AT91_USART_RXD1 AT91_PIN(0,0,21) // USART 1 Receive Data +#define AT91_USART_TXD1 AT91_PIN(0,0,22) // USART 1 Transmit Data +#define AT91_USART_SCK1 AT91_PIN(0,0,23) // USART 1 Serial Clock +#define AT91_USART_RTS1 AT91_PIN(0,0,24) // USART 1 Ready To Send +#define AT91_USART_CTS1 AT91_PIN(0,0,25) // USART 1 Clear To Send +#define AT91_USART_DVD1 AT91_PIN(0,0,26) // USART 1 Data Carrier Detect +#define AT91_USART_DTR1 AT91_PIN(0,0,27) // USART 1 Data Terminal Ready +#define AT91_USART_DSR1 AT91_PIN(0,0,28) // USART 1 Data Set Ready +#define AT91_USART_RI1 AT91_PIN(0,0,29) // USART 2 Ring Indicator +#define AT91_INT_IRQ1 AT91_PIN(0,0,30) // Interrupt Request 1 +#define AT91_SPI_NPCS1 AT91_PIN(0,0,31) // SPI Chip Select 1 +#endif + +#define AT91_TC_TI0A0 AT91_PIN(0,1, 0) // Timer/Counter 0 IO Line A +#define AT91_TC_TI0B0 AT91_PIN(0,1, 1) // Timer/Counter 0 IO Line B +#define AT91_USART_SCK0 AT91_PIN(0,1, 2) // USART 0 Serial Clock +#define AT91_SPI_NPCS3 AT91_PIN(0,1, 3) // SPI Chip Select 3 +#define AT91_TC_TCLK0 AT91_PIN(0,1, 4) // Timer/Counter 0 Clock Input +#define AT91_SPI_NPCS3X AT91_PIN(0,1, 5) // SPI Chip Select 3 (again) +#define AT91_PCK_PCK0 AT91_PIN(0,1, 6) // Programmable Clock Output 0 +#define AT91_PWM_PWM3 AT91_PIN(0,1, 7) // Pulse Width Modulation #3 +#define AT91_ADC_ADTRG AT91_PIN(0,1, 8) // ADC Trigger +#define AT91_SPI_NPCS1X AT91_PIN(0,1, 9) // SPI Chip Select 1 +#define AT91_SPI_NPCS2 AT91_PIN(0,1,10) // SPI Chip Select 2 +#define AT91_PWM_PWM0X AT91_PIN(0,1,11) // Pulse Width Modulation #0 +#define AT91_PIO_PWM_PWM1X AT91_PIN(0,1,12) // Pulse Width Modulation #1 +#define AT91_PIO_PWM_PWM2X AT91_PIN(0,1,13) // Pulse Width Modulation #2 +#define AT91_PIO_PWM_PWM4X AT91_PIN(0,1,14) // Pulse Width Modulation #4 +#define AT91_TC_TIOA1 AT91_PIN(0,1,15) // Timer/Counter 1 IO Line A +#define AT91_TC_TIOB1 AT91_PIN(0,1,16) // Timer/Counter 1 IO Line B +#define AT91_PCK_PCK1 AT91_PIN(0,1,17) // Programmable Clock Output 1 +#define AT91_PCK_PCK2 AT91_PIN(0,1,18) // Programmable Clock Output 2 +#define AT91_INT_FIQ AT91_PIN(0,1,19) // Fast Interrupt Request +#define AT91_INT_IRQ0 AT91_PIN(0,1,20) // Interrupt Request 0 +#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32) +#define AT91_PCK_PCK1X AT91_PIN(0,1,21) // Programmable Clock Output 1 +#define AT91_SPI_NPCS3XX AT91_PIN(0,1,22) // SPI Chip Select 3 (yet again) +#define AT91_PWM_PWM0XX AT91_PIN(0,1,23) // Pulse Width Modulation #0 +#define AT91_PWM_PWM1XX AT91_PIN(0,1,24) // Pulse Width Modulation #1 +#define AT91_PWM_PWM2XX AT91_PIN(0,1,25) // Pulse Width Modulation 2 +#define AT91_TC_TIOA2 AT91_PIN(0,1,26) // Timer/Counter 2 IO Line A +#define AT91_TC_TIOB2 AT91_PIN(0,1,27) // Timer/Counter 2 IO Line B +#define AT91_TC_TCLK1 AT91_PIN(0,1,28) // External Clock Input 1 +#define AT91_TC_TCLK2 AT91_PIN(0,1,29) // External Clock Input 2 +#define AT91_SPI_NPCS2X AT91_PIN(0,1,30) // SPI Chip Select 2 (again) +#define AT91_PCK_PCK2X AT91_PIN(0,1,31) // Programmable Clock Output 2 +#endif //!defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32) + +// PIO Peripheral A #define AT91_PIO_PSR_PWM0 0x00000001 // Pulse Width Modulation 0 #define AT91_PIO_PSR_PWM1 0x00000002 // Pulse Width Modulation 1 #define AT91_PIO_PSR_PWM2 0x00000004 // Pulse Width Modulation 2 @@ -240,12 +430,12 @@ #define AT91_PIO_PSR_MISO 0x00001000 // SPI Input #define AT91_PIO_PSR_MOIS 0x00002000 // SPI Output #define AT91_PIO_PSR_SPCK 0x00004000 // SPI clock -#define AT91_PIO_PSR_TF 0x00008000 // Transmit Frame Sync -#define AT91_PIO_PSR_TK 0x00010000 // Transmit Clock -#define AT91_PIO_PSR_TD 0x00020000 // Transmit Data -#define AT91_PIO_PSR_RD 0x00040000 // Receive Data -#define AT91_PIO_PSR_RK 0x00080000 // Receive Clock -#define AT91_PIO_PSR_RF 0x00100000 // Receive Frame Sync +#define AT91_PIO_PSR_TF 0x00008000 // S2C Transmit Frame Sync +#define AT91_PIO_PSR_TK 0x00010000 // S2C Transmit Clock +#define AT91_PIO_PSR_TD 0x00020000 // S2C Transmit Data +#define AT91_PIO_PSR_RD 0x00040000 // S2C Receive Data +#define AT91_PIO_PSR_RK 0x00080000 // S2C Receive Clock +#define AT91_PIO_PSR_RF 0x00100000 // S2C Receive Frame Sync #if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32) #define AT91_PIO_PSR_RXD1 0x00200000 // USART 1 Receive Data #define AT91_PIO_PSR_TXD1 0x00400000 // USART 1 Transmit Data @@ -257,10 +447,10 @@ #define AT91_PIO_PSR_DSR1 0x10000000 // USART 1 Data Set Ready #define AT91_PIO_PSR_RI1 0x20000000 // USART 2 Ring Indicator #define AT91_PIO_PSR_IRQ1 0x40000000 // Interrupt Request 1 -#define AT01_PIO_PSR_NPCS1 0x80000000 // SPI Chip Select 1 +#define AT91_PIO_PSR_NPCS1 0x80000000 // SPI Chip Select 1 #endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s64) -// PIOB +// PIO Peripheral B #define AT91_PIO_PSR_TIOA0 0x00000001 // Timer/Counter 0 IO Line A #define AT91_PIO_PSR_TIOB0 0x00000002 // Timer/Counter 0 IO Line B #define AT91_PIO_PSR_SCK0 0x00000004 // USART 0 Serial Clock @@ -270,7 +460,7 @@ #define AT91_PIO_PSR_PCK0 0x00000040 // Programmable Clock Output 0 #define AT91_PIO_PSR_PWM3 0x00000080 // Pulse Width Modulation #3 #define AT91_PIO_PSR_ADTRG 0x00000100 // ADC Trigger -#define AT91_PIO_PSR_NPCS1 0x00000200 // SPI Chip Select 1 +#define AT91_PIO_PSR_NPCS1X 0x00000200 // SPI Chip Select 1 (again) #define AT91_PIO_PSR_NPCS2 0x00000400 // SPI Chip Select 2 #define AT91_PIO_PSR_PWMOX 0x00000800 // Pulse Width Modulation #0 (again) #define AT91_PIO_PSR_PWM1X 0x00001000 // Pulse Width Modulation #1 (again) @@ -295,8 +485,255 @@ #define AT91_PIO_PSR_NPCS2X 0x40000000 // SPI Chip Select 2 (again) #define AT91_PIO_PSR_PCK2X 0x80000000 // Programmable Clock Output 2(again) #endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s64) +#endif // CYGHWR_HAL_ARM_AT91SAM7S + +#ifdef CYGHWR_HAL_ARM_AT91SAM7X + +// PIO Controller A, peripheral A +#define AT91_USART_RXD0 AT91_PIN(0,0, 0) // USART 0 Receive Data +#define AT91_USART_TXD0 AT91_PIN(0,0, 1) // USART 0 Transmit Data +#define AT91_USART_SCK0 AT91_PIN(0,0, 2) // USART 0 Serial Clock +#define AT91_USART_RTS0 AT91_PIN(0,0, 3) // USART 0 Request To Send +#define AT91_USART_CTS0 AT91_PIN(0,0, 4) // USART 0 Clear To Send +#define AT91_USART_RXD1 AT91_PIN(0,0, 5) // USART 1 Receive Data +#define AT91_USART_TXD1 AT91_PIN(0,0, 6) // USART 1 Transmit Data +#define AT91_USART_SCK1 AT91_PIN(0,0, 7) // USART 1 Serial Clock +#define AT91_USART_RTS1 AT91_PIN(0,0, 8) // USART 1 Request To Send +#define AT91_USART_CTS1 AT91_PIN(0,0, 9) // USART 1 Clear To Send +#define AT91_TWI_TWD AT91_PIN(0,0,10) // Two Wire Data +#define AT91_TWI_TWCK AT91_PIN(0,0,11) // Two Wire Clock +#define AT91_SPI_NPCS0 AT91_PIN(0,0,12) // SPI 0 Chip Select 0 +#define AT91_SPI_NPCS1 AT91_PIN(0,0,13) // SPI 0 Chip Select 1 +#define AT91_SPI_NPCS2 AT91_PIN(0,0,14) // SPI 0 Chip Select 2 +#define AT91_SPI_NPCS3 AT91_PIN(0,0,15) // SPI 0 Chip Select 3 +#define AT91_SPI_MISO AT91_PIN(0,0,16) // SPI 0 Master In Slave Out +#define AT91_SPI_MOIS AT91_PIN(0,0,17) // SPI 0 Master Out Slave In +#define AT91_SPI_SPCK AT91_PIN(0,0,18) // SPI 0 Clock +#define AT91_CAN_CANRX AT91_PIN(0,0,19) // CAN Receive +#define AT91_CAN_CANTX AT91_PIN(0,0,20) // CAN Transmit +#define AT91_SSC_TF AT91_PIN(0,0,21) // SSC Transmit Frame Sync +#define AT91_S2C_TK AT91_PIN(0,0,22) // SSC Transmit Clock +#define AT91_S2C_TD AT91_PIN(0,0,23) // SSC Transmit Data +#define AT91_S2C_RD AT91_PIN(0,0,24) // SSC Receive Data +#define AT91_S2C_RK AT91_PIN(0,0,25) // SSC Receive Clock +#define AT91_S2C_RF AT91_PIN(0,0,26) // SSC Receive Frame Sync +#define AT91_DBG_DRXD AT91_PIN(0,0,27) // DBGU Receive Data +#define AT91_DBG_DTXD AT91_PIN(0,0,28) // DBGU Transmit Data +#define AT91_INT_FIQ AT91_PIN(0,0,29) // Fast Interrupt Request +#define AT91_INT_IRQ0 AT91_PIN(0,0,39) // Interrupt Request 0 + +//PIO controller A, peripheral B +#define AT91_SPI1_NPCS1 AT91_PIN(0,1, 2) // SPI 1 Chip Select 1 +#define AT91_SPI1_NPCS2 AT91_PIN(0,1, 3) // SPI 1 Chip Select 2 +#define AT91_SPI1_NPCS3 AT91_PIN(0,1, 4) // SPI 1 Chip Select 3 +#define AT91_SPI_NPCS1X AT91_PIN(0,1, 7) // SPI 0 Chip Select 1 +#define AT91_SPI_NPCS2X AT91_PIN(0,1, 8) // SPI 0 Chip Select 2 +#define AT91_SPI_NPCS3X AT91_PIN(0,1, 9) // SPI 0 Chip Select 3 +#define AT91_PCK_PCK1 AT91_PIN(0,1,13) // Programmable Clock Output 1 +#define AT91_INT_IRQ1 AT91_PIN(0,1,14) // Interrupt Request 1 +#define AT91_TC_TCLK1 AT91_PIN(0,1,15) // Timer/Counter 1 Clock Input +#define AT91_SPI1_NPCS0 AT91_PIN(0,1,21) // SPI 1 Chip Select 0 +#define AT91_SPI1_SPCK AT91_PIN(0,1,22) // SPI 1 Clock +#define AT91_SPI1_MOSI AT91_PIN(0,1,23) // SPI 1 Master Out Slave In +#define AT91_SPI1_MISO AT91_PIN(0,1,24) // SPI 0 Master In Slave Out +#define AT91_SPI1_NPCS1X AT91_PIN(0,1,25) // SPI 1 Chip Select 1 +#define AT91_SPI1_NPCS2X AT91_PIN(0,1,26) // SPI 1 Chip Select 2 +#define AT91_PCK_PCK3 AT91_PIN(0,1,27) // Programmable Clock Output 3 +#define AT91_SPI1_NPCS3X AT91_PIN(0,1,29) // SPI 1 Chip Select 3 +#define AT91_PCK_PCK2 AT91_PIN(0,1,30) // Programmable Clock Output 2 + +//PIO Controller B, Peripheral A +#define AT91_EMAC_EREFCK AT91_PIN(1,0, 0) // EMAC Reference Clock +#define AT91_EMAC_ETXEN AT91_PIN(1,0, 1) // EMAC Transmit Enable +#define AT91_EMAC_ETX0 AT91_PIN(1,0, 2) // EMAC Transmit Data 0 +#define AT91_EMAC_ETX1 AT91_PIN(1,0, 3) // EMAC Transmit Data 1 +#define AT91_EMAC_ECRS AT91_PIN(1,0, 4) // EMAC Carrier Sense +#define AT91_EMAC_ERX0 AT91_PIN(1,0, 5) // EMAC Receive Data 0 +#define AT91_EMAC_ERX1 AT91_PIN(1,0, 6) // EMAC Receive Data 1 +#define AT91_EMAC_ERXER AT91_PIN(1,0, 7) // EMAC Receive Error +#define AT91_EMAC_EMDC AT91_PIN(1,0, 8) // EMAC Management Data Clock +#define AT91_EMAC_EMDIO AT91_PIN(1,0, 9) // EMAC Management Data IO +#define AT91_EMAC_ETX2 AT91_PIN(1,0,10) // EMAC Transmit Data 2 +#define AT91_EMAC_ETX3 AT91_PIN(1,0,11) // EMAC Transmit Data 3 +#define AT91_EMAC_ETXER AT91_PIN(1,0,12) // EMAC Transmit Coding Error +#define AT91_EMAC_ERX2 AT91_PIN(1,0,13) // EMAC Receive Data 2 +#define AT91_EMAC_ERX3 AT91_PIN(1,0,14) // EMAC Receive Data 3 +#define AT91_EMAC_ECRSDV AT91_PIN(1,0,15) // EMAC Carrier Sense And Data Valid +#define AT91_EMAC_ERXDV AT91_PIN(1,0,15) // EMAC Receive Data Valid +#define AT91_EMAC_ECOL AT91_PIN(1,0,16) // EMAC Collision Detected +#define AT91_EMAC_ERXCK AT91_PIN(1,0,17) // EMAC Receive Clock +#define AT91_EMAC_EF100 AT91_PIN(1,0,18) // EMAC Force 100Mb/s +#define AT91_PWM_PWM0 AT91_PIN(1,0,19) // Pulse Width Modulation #0 +#define AT91_PWM_PWM1 AT91_PIN(1,0,20) // Pulse Width Modulation #1 +#define AT91_PWM_PWM2 AT91_PIN(1,0,21) // Pulse Width Modulation #2 +#define AT91_PWM_PWM3 AT91_PIN(1,0,22) // Pulse Width Modulation #3 +#define AT91_TC_TIOA0 AT91_PIN(1,0,23) // Timer/Counter 0 IO Line A +#define AT91_TC_TIOB0 AT91_PIN(1,0,24) // Timer/Counter 0 IO Line B +#define AT91_TC_TIOA1 AT91_PIN(1,0,25) // Timer/Counter 1 IO Line A +#define AT91_TC_TIOB1 AT91_PIN(1,0,26) // Timer/Counter 1 IO Line B +#define AT91_TC_TIOA2 AT91_PIN(1,0,27) // Timer/Counter 2 IO Line A +#define AT91_TC_TIOB2 AT91_PIN(1,0,28) // Timer/Counter 2 IO Line B +#define AT91_PCK_PCK1X AT91_PIN(1,0,29) // Programmable Clock Output 1 +#define AT91_PCK_PCK2X AT91_PIN(1,0,30) // Programmable Clock Output 2 + +//PIO Controller B Peripheral B +#define AT91_PCK_PCK0 AT91_PIN(1,1, 0) // Programmable Clock Output 0 +#define AT91_SPI1_NPCS1XX AT91_PIN(1,1,10) // SPI 1 Chip Select 1 +#define AT91_SPI1_NPCS2XX AT91_PIN(1,1,11) // SPI 1 Chip Select 2 +#define AT91_TC_TCLK0 AT91_PIN(1,1,12) // Timer/Counter 0 Clock Input +#define AT91_SPI_NPCS1XX AT91_PIN(1,1,13) // SPI 0 Chip Select 1 +#define AT91_SPI_NPCS2XX AT91_PIN(1,1,14) // SPI 0 Chip Select 2 +#define AT91_SPI1_NPCS3XX AT91_PIN(1,1,16) // SPI 1 Chip Select 3 +#define AT91_SPI_NPCS3XX AT91_PIN(1,1,17) // SPI 0 Chip Select 3 +#define AT91_ADC_ADTRG AT91_PIN(1,1,18) // ADC Trigger +#define AT91_TC_TCLK1X AT91_PIN(1,1,19) // Timer/Counter 1 Clock Input +#define AT91_PCK_PCK0X AT91_PIN(1,1,20) // Programmable Clock Output 0 +#define AT91_PCK_PCK1XX AT91_PIN(1,1,21) // Programmable Clock Output 1 +#define AT91_PCK_PCK2XX AT91_PIN(1,1,22) // Programmable Clock Output 2 +#define AT91_USART_DCD1 AT91_PIN(1,1,23) // USART 1 Data Carrier Detect +#define AT91_USART_DSR1 AT91_PIN(1,1,24) // USART 1 Data Set Ready +#define AT91_USART_DTR1 AT91_PIN(1,1,25) // USART 1 Data Terminal Ready +#define AT91_USART_RI1 AT91_PIN(1,1,26) // USART 1 Ring Indication +#define AT91_PWM_PWM0X AT91_PIN(1,1,27) // Pulse Width Modulation #0 +#define AT91_PWM_PWM1X AT91_PIN(1,1,28) // Pulse Width Modulation #1 +#define AT91_PWM_PWM2X AT91_PIN(1,1,29) // Pulse Width Modulation #2 +#define AT91_PWM_PWM3X AT91_PIN(1,1,30) // Pulse Width Modulation #3 + +// PIO Controller A, peripheral A +#define AT91_PIO_PSR_RXD0 (1<< 0) // USART 0 Receive Data +#define AT91_PIO_PSR_TXD0 (1<< 1) // USART 0 Transmit Data +#define AT91_PIO_PSR_SCK0 (1<< 2) // USART 0 Serial Clock +#define AT91_PIO_PSR_RTS0 (1<< 3) // USART 0 Request To Send +#define AT91_PIO_PSR_CTS0 (1<< 4) // USART 0 Clear To Send +#define AT91_PIO_PSR_RXD1 (1<< 5) // USART 1 Receive Data +#define AT91_PIO_PSR_TXD1 (1<< 6) // USART 1 Transmit Data +#define AT91_PIO_PSR_SCK1 (1<< 7) // USART 1 Serial Clock +#define AT91_PIO_PSR_RTS1 (1<< 8) // USART 1 Request To Send +#define AT91_PIO_PSR_CTS1 (1<< 9) // USART 1 Clear To Send +#define AT91_PIO_PSR_TWD (1<<10) // Two Wire Data +#define AT91_PIO_PSR_TWCK (1<<11) // Two Wire Clock +#define AT91_PIO_PSR_SPI_NPCS0 (1<<12) // SPI 0 Chip Select 0 +#define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1 +#define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2 +#define AT91_PIO_PSR_SPI_NPCS3 (1<<15) // SPI 0 Chip Select 3 +#define AT91_PIO_PSR_SPI_MISO (1<<16) // SPI 0 Master In Slave Out +#define AT91_PIO_PSR_SPI_MOSI (1<<17) // SPI 0 Master Out Slave In +#define AT91_PIO_PSR_SPI_SPCK (1<<18) // SPI 0 Clock +#define AT91_PIO_PSR_CANRX (1<<19) // CAN Receive +#define AT91_PIO_PSR_CANTX (1<<20) // CAN Transmit +#define AT91_PIO_PSR_TF (1<<21) // SSC Transmit Frame Sync +#define AT91_PIO_PSR_TK (1<<22) // SSC Transmit Clock +#define AT91_PIO_PSR_TD (1<<23) // SSC Transmit Data +#define AT91_PIO_PSR_RD (1<<24) // SSC Receive Data +#define AT91_PIO_PSR_RK (1<<25) // SSC Receive Clock +#define AT91_PIO_PSR_RF (1<<26) // SSC Receive Frame Sync +#define AT91_PIO_PSR_DRXD (1<<27) // DBGU Receive Data +#define AT91_PIO_PSR_DTXD (1<<28) // DBGU Transmit Data +#define AT91_PIO_PSR_FIQ (1<<29) // Fast Interrupt Request +#define AT91_PIO_PSR_IRQ0 (1<<30) // Interrupt Request 0 + +//PIO controller A, peripheral B +#define AT91_PIO_PSR_SPI1_NPCS1 (1<< 2) // SPI 1 Chip Select 1 +#define AT91_PIO_PSR_SPI1_NPCS2 (1<< 3) // SPI 1 Chip Select 2 +#define AT91_PIO_PSR_SPI1_NPCS3 (1<< 4) // SPI 1 Chip Select 3 +#define AT91_PIO_PSR_SPI_NPCS1X (1<< 7) // SPI 0 Chip Select 1 +#define AT91_PIO_PSR_SPI_NPCS2X (1<< 8) // SPI 0 Chip Select 2 +#define AT91_PIO_PSR_SPI_NPCS3X (1<< 9) // SPI 0 Chip Select 3 +#define AT91_PIO_PSR_PCK1 (1<<13) // Programmable Clock Output 1 +#define AT91_PIO_PSR_IRQ1 (1<<14) // Interrupt Request 1 +#define AT91_PIO_PSR_TCLK1 (1<<15) // Timer/Counter 1 Clock Input +#define AT91_PIO_PSR_SPI1_NPCS0 (1<<21) // SPI 1 Chip Select 0 +#define AT91_PIO_PSR_SPI1_SPCK (1<<22) // SPI 1 Clock +#define AT91_PIO_PSR_SPI1_MOSI (1<<23) // SPI 1 Master Out Slave In +#define AT91_PIO_PSR_SPI1_MISO (1<<24) // SPI 0 Master In Slave Out +#define AT91_PIO_PSR_SPI1_NPCS1X (1<<25) // SPI 1 Chip Select 1 +#define AT91_PIO_PSR_SPI1_NPCS2X (1<<26) // SPI 1 Chip Select 2 +#define AT91_PIO_PSR_PCK3 (1<<27) // Programmable Clock Output 3 +#define AT91_PIO_PSR_SPI1_NPCS3X (1<<29) // SPI 1 Chip Select 3 +#define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2 + +//PIO Controller B, Peripheral A +#define AT91_PIO_PSR_EREFCK (1<< 0) // EMAC Reference Clock +#define AT91_PIO_PSR_ETXEN (1<< 1) // EMAC Transmit Enable +#define AT91_PIO_PSR_ETX0 (1<< 2) // EMAC Transmit Data 0 +#define AT91_PIO_PSR_ETX1 (1<< 3) // EMAC Transmit Data 1 +#define AT91_PIO_PSR_ECRS (1<< 4) // EMAC Carrier Sense +#define AT91_PIO_PSR_ERX0 (1<< 5) // EMAC Receive Data 0 +#define AT91_PIO_PSR_ERX1 (1<< 6) // EMAC Receive Data 1 +#define AT91_PIO_PSR_ERXER (1<< 7) // EMAC Receive Error +#define AT91_PIO_PSR_EMDC (1<< 8) // EMAC Management Data Clock +#define AT91_PIO_PSR_EMDIO (1<< 9) // EMAC Management Data IO +#define AT91_PIO_PSR_ETX2 (1<<10) // EMAC Transmit Data 2 +#define AT91_PIO_PSR_ETX3 (1<<11) // EMAC Transmit Data 3 +#define AT91_PIO_PSR_ETXER (1<<12) // EMAC Transmit Coding Error +#define AT91_PIO_PSR_ERX2 (1<<13) // EMAC Receive Data 2 +#define AT91_PIO_PSR_ERX3 (1<<14) // EMAC Receive Data 3 +#define AT91_PIO_PSR_ECRSDV (1<<15) // EMAC Carrier Sense And Data Valid +#define AT91_PIO_PSR_ECOL (1<<16) // EMAC Collision Detected +#define AT91_PIO_PSR_ERXCK (1<<17) // EMAC Receive Clock +#define AT91_PIO_PSR_EF100 (1<<18) // EMAC Force 100Mb/s +#define AT91_PIO_PSR_PWM0 (1<<19) // Pulse Width Modulation #0 +#define AT91_PIO_PSR_PWM1 (1<<20) // Pulse Width Modulation #1 +#define AT91_PIO_PSR_PWM2 (1<<21) // Pulse Width Modulation #2 +#define AT91_PIO_PSR_PWM3 (1<<22) // Pulse Width Modulation #3 +#define AT91_PIO_PSR_TIOA0 (1<<23) // Timer/Counter 0 IO Line A +#define AT91_PIO_PSR_TIOB0 (1<<24) // Timer/Counter 0 IO Line B +#define AT91_PIO_PSR_TIOA1 (1<<25) // Timer/Counter 1 IO Line A +#define AT91_PIO_PSR_TIOB1 (1<<26) // Timer/Counter 1 IO Line B +#define AT91_PIO_PSR_TIOA2 (1<<27) // Timer/Counter 2 IO Line A +#define AT91_PIO_PSR_TIOB2 (1<<28) // Timer/Counter 2 IO Line B +#define AT91_PIO_PSR_PCK1X (1<<29) // Programmable Clock Output 1 +#define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2 + +//PIO Controller B Peripheral B +#define AT91_PIO_PSR_PCK0 (1<< 0) // Programmable Clock Output 0 +#define AT91_PIO_PSR_SPI1_NPCS1XX (1<<10) // SPI 1 Chip Select 1 +#define AT91_PIO_PSR_SPI1_NPCS2XX (1<<11) // SPI 1 Chip Select 2 +#define AT91_PIO_PSR_TCLK0 (1<<12) // Timer/Counter 0 Clock Input +#define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1 +#define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2 +#define AT91_PIO_PSR_SPI1_NPCS3XX (1<<16) // SPI 1 Chip Select 3 +#define AT91_PIO_PSR_SPI_NPCS3XX (1<<17) // SPI 0 Chip Select 3 +#define AT91_PIO_PSR_ADTRG (1<<18) // ADC Trigger +#define AT91_PIO_PSR_TCLK1X (1<<19) // Timer/Counter 1 Clock Input +#define AT91_PIO_PSR_PCK0X (1<<20) // Programmable Clock Output 0 +#define AT91_PIO_PSR_PCK1XX (1<<21) // Programmable Clock Output 1 +#define AT91_PIO_PSR_PCK2X (1<<22) // Programmable Clock Output 2 +#define AT91_PIO_PSR_DCD1 (1<<23) // USART 1 Data Carrier Detect +#define AT91_PIO_PSR_DSR1 (1<<24) // USART 1 Data Set Ready +#define AT91_PIO_PSR_DTR1 (1<<25) // USART 1 Data Terminal Ready +#define AT91_PIO_PSR_RI1 (1<<26) // USART 1 Ring Indication +#define AT91_PIO_PSR_PWM0X (1<<27) // Pulse Width Modulation #0 +#define AT91_PIO_PSR_PWM1X (1<<28) // Pulse Width Modulation #1 +#define AT91_PIO_PSR_PWM2X (1<<29) // Pulse Width Modulation #2 +#define AT91_PIO_PSR_PWM3X (1<<30) // Pulse Width Modulation #3 +#endif + +#ifdef CYGHWR_HAL_ARM_AT91SAM7XC +#error Sorry, still missing. Happy typing +#endif #else +#define AT91_TC_TCLK0 AT91_PIN(0,0, 0) // Timer #0 clock +#define AT91_TC_TIOA0 AT91_PIN(0,0, 1) // Timer #0 signal A +#define AT91_TC_TIOB0 AT91_PIN(0,0, 2) // Timer #0 signal B +#define AT91_TC_TCLK1 AT91_PIN(0,0, 3) // Timer #1 clock +#define AT91_TC_TIOA1 AT91_PIN(0,0, 4) // Timer #1 signal A +#define AT91_TC_TIOB1 AT91_PIN(0,0, 5) // Timer #1 signal B +#define AT91_TC_TCLK2 AT91_PIN(0,0, 6) // Timer #2 clock +#define AT91_TC_TIOA2 AT91_PIN(0,0, 7) // Timer #2 signal A +#define AT91_TC_TIOB2 AT91_PIN(0,0, 8) // Timer #2 signal B +#define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // IRQ #0 +#define AT91_INT_IRQ1 AT91_PIN(0,0,10) // IRQ #1 +#define AT91_INT_IRQ2 AT91_PIN(0,0,11) // IRQ #2 +#define AT91_INT_FIQ AT91_PIN(0,0,12) // FIQ +#define AT91_USART_SCK0 AT91_PIN(0,0,13) // Serial port #0 clock +#define AT91_USART_TXD0 AT91_PIN(0,0,14) // Serial port #0 TxD +#define AT91_USART_RXD0 AT91_PIN(0,0,15) // Serial port #0 RxD +#define AT91_USART_SCK1 AT91_PIN(0,0,20) // Serial port #1 clock +#define AT91_USART_TXD1 AT91_PIN(0,0,21) // Serial port #1 TxD +#define AT91_USART_RXD1 AT91_PIN(0,0,22) // Serial port #1 RxD +#define AT91_CLK_MCKO AT91_PIN(0,0,25) // Master clock out #define AT91_PIO_PSR_TCLK0 0x00000001 // Timer #0 clock #define AT91_PIO_PSR_TIOA0 0x00000002 // Timer #0 signal A @@ -330,7 +767,6 @@ #define AT91_PIO_PSR_CS6_A21 0x20000000 // Chip select #6 or A21 #define AT91_PIO_PSR_CS5_A22 0x40000000 // Chip select #5 or A22 #define AT91_PIO_PSR_CS4_A23 0x80000000 // Chip select #4 or A23 - #endif #define AT91_PIO_OER 0x10 // Output enable @@ -348,7 +784,7 @@ #define AT91_PIO_IMR 0x48 // Interrupt mask #define AT91_PIO_ISR 0x4C // Interrupt status -#ifdef CYGHWR_HAL_ARM_AT91SAM7S +#if defined(CYGHWR_HAL_ARM_AT91SAM7) #define AT91_PIO_MDER 0x50 // Multi-drive Enable Register #define AT91_PIO_MDDR 0x54 // Multi-drive Disable Register #define AT91_PIO_MDSR 0x58 // Multi-drive Status Register @@ -361,7 +797,8 @@ #define AT91_PIO_OWER 0xa0 // Output Write Enable Register #define AT91_PIO_OWDR 0xa4 // Output Write Disable Register #define AT91_PIO_OWSR 0xa8 // Output Write Status Register -#endif // CYGHWR_HAL_ARM_AT91SAM7S +#endif // CYGHWR_HAL_ARM_AT91SAM7 + //============================================================================= // Advanced Interrupt Controller (AIC) @@ -451,12 +888,12 @@ #define AT91_AIC_EOI 0x130 #define AT91_AIC_SVR 0x134 -#ifdef CYGHWR_HAL_ARM_AT91SAM7S +#ifdef CYGHWR_HAL_ARM_AT91SAM7 #define AT91_AIC_DCR 0x138 // Debug Control Register #define AT91_AIC_FFER 0x140 // Fast Forcing Enable Register #define AT91_AIC_FFDR 0x144 // Fast Forcing Enable Register #define AT91_AIC_FFSR 0x148 // Fast Forcing Enable Register -#endif +#endif // CYGHWR_HAL_ARM_AT91SAM7 //============================================================================= // Timer / counter @@ -655,7 +1092,7 @@ #elif defined(CYGHWR_HAL_ARM_AT91_M42800A) || \ defined(CYGHWR_HAL_ARM_AT91_M55800A) || \ - defined(CYGHWR_HAL_ARM_AT91SAM7S) + defined(CYGHWR_HAL_ARM_AT91SAM7) // (Advanced) Power Management @@ -817,7 +1254,32 @@ #define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0 #define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1 #define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2 -#else + +#elif defined(CYGHWR_HAL_ARM_AT91SAM7X) +#define AT91_PMC_SCER_PCK (1 << 0) // Processor Clock +#define AT91_PMC_SCER_UDP (1 << 7) // USB Device Clock +#define AT91_PMC_SCER_PCK0 (1 << 8) // Programmable Clock Output +#define AT91_PMC_SCER_PCK1 (1 << 9) // Programmable Clock Output +#define AT91_PMC_SCER_PCK2 (1 << 10) // Programmable Clock Output +#define AT91_PMC_SCER_PCK3 (1 << 11) // Programmable Clock Output + +#define AT91_PMC_PCER_PIOA (1 << 2) // Parallel IO Controller +#define AT91_PMC_PCER_PIOB (1 << 3) // Parallel IO Controller +#define AT91_PMC_PCER_SPI (1 << 4) // Serial Peripheral Interface +#define AT91_PMC_PCER_SPI1 (1 << 5) // Serial Peripheral Interface +#define AT91_PMC_PCER_US0 (1 << 6) // USART 0 +#define AT91_PMC_PCER_US1 (1 << 7) // USART 1 +#define AT91_PMC_PCER_SSC (1 << 8) // Serial Synchronous Controller +#define AT91_PMC_PCER_TWI (1 << 9) // Two-Wire Interface +#define AT91_PMC_PCER_PWMC (1 <<10) // PWM Controller +#define AT91_PMC_PCER_UDP (1 <<11) // USB Device Port +#define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0 +#define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1 +#define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2 +#define AT91_PMC_PCER_CAN (1 <<15) // Controller Area Network +#define AT91_PMC_PCER_EMAC (1 <<16) // Ethernet MAC +#define AT91_PMC_PCER_ADC (1 <<17) // Analog-to-Digital Conveter +#else // Something unknown #error Unknown AT91 variant @@ -869,7 +1331,7 @@ #define AT91_SPI_TDR 0x0C // Transmit Data Register #define AT91_SPI_SR 0x10 // Status Register #define AT91_SPI_SR_RDRF 0x00000001 // Receive Data Register Full -#define AT91_SPI_SR_TDRE 0x00000002 // Transmit Data Register Empty +#define AT91_SPI_SR_TDRE 0x00000002 // Tx Data Register Empty #define AT91_SPI_SR_MODF 0x00000004 // Mode Fault Error #define AT91_SPI_SR_OVRES 0x00000008 // Overrun Error Status #define AT91_SPI_SR_ENDRX 0x00000010 // End of Receiver Transfer @@ -892,6 +1354,13 @@ #ifndef AT91_SPI_TCR #define AT91_SPI_TCR 0x2C // Transmit Counter Register #endif + +// PDC Control register bits +#define AT91_SPI_PTCR_RXTEN (1 << 0) +#define AT91_SPI_PTCR_RXTDIS (1 << 1) +#define AT91_SPI_PTCR_TXTEN (1 << 8) +#define AT91_SPI_PTCR_TXTDIS (1 << 9) + #define AT91_SPI_CSR0 0x30 // Chip Select Register 0 #define AT91_SPI_CSR1 0x34 // Chip Select Register 1 #define AT91_SPI_CSR2 0x38 // Chip Select Register 2 @@ -911,27 +1380,11 @@ #define AT91_SPI_CSR_SCBR(x) (((x)&0xFF)<<8) // Serial Clock Baud Rate #define AT91_SPI_CSR_DLYBS(x) (((x)&0xFF)<<16) // Delay Before SPCK #define AT91_SPI_CSR_DLYBCT(x) (((x)&0xFF)<<24) // Delay Between two transfers - -#if defined(CYGHWR_HAL_ARM_AT91_M55800A) - -#define AT91_SPI_PIO AT91_PIOA -#define AT91_SPI_PIO_NPCS(x) (((x)&0x0F)<<26) -#endif - -#if defined(CYGHWR_HAL_ARM_AT91SAM7S) - -#define AT91_SPI_PIO AT91_PIOA -#define AT91_SPI_PIO_NPCS(x) \ - ( (x & (1 << 0) ? AT91_PIO_PSR_NPCS0 : 0) | \ - (x & (1 << 1) ? AT91_PIO_PSR_NPCS1 : 0) | \ - (x & (1 << 2) ? AT91_PIO_PSR_NPCS2 : 0) | \ - (x & (1 << 3) ? AT91_PIO_PSR_NPCS3 : 0)) -#endif //============================================================================= // Watchdog Timer Controller -#if defined(CYGHWR_HAL_ARM_AT91SAM7S) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) #ifndef AT91_WDTC #define AT91_WDTC 0xFFFFFD40 @@ -951,12 +1404,12 @@ #define AT91_WDTC_WDSR 0x08 // Watchdog Status Register #define AT91_WDTC_WDSR_UNDER (1 << 0) // Underflow has occurred #define AT91_WDTC_WDSR_ERROR (1 << 1) // Error has occurred -#endif //CYGHWR_HAL_ARM_AT91SAM7S +#endif //CYGHWR_HAL_ARM_AT91SAM7 //============================================================================= // Reset Controller -#if defined(CYGHWR_HAL_ARM_AT91SAM7S) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) #ifndef AT91_RST #define AT91_RST 0xFFFFFD00 @@ -989,7 +1442,7 @@ //============================================================================= // Memory Controller -#if defined(CYGHWR_HAL_ARM_AT91SAM7S) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) #ifndef AT91_MC #define AT91_MC 0xFFFFFF00 @@ -1033,7 +1486,7 @@ //============================================================================= // Debug Unit -#if defined(CYGHWR_HAL_ARM_AT91SAM7S) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) #ifndef AT91_DBG #define AT91_DBG 0xFFFFF200 @@ -1149,7 +1602,7 @@ //============================================================================= // Periodic Interval Timer Controller -#if defined(CYGHWR_HAL_ARM_AT91SAM7S) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) #ifndef AT91_PITC #define AT91_PITC 0xfffffd30 @@ -1157,7 +1610,7 @@ #define AT91_PITC_PIMR 0x00 // Period Interval Mode Register #define AT91_PITC_PIMR_PITEN (1 << 24) // Periodic Interval Timer Enable -#define AT91_PITC_PIMR_PITIEN (1 << 25) // Periodic Interval Timer Interrupt Enable +#define AT91_PITC_PIMR_PITIEN (1 << 25) // Periodic Interval Timer Intr Enable #define AT91_PITC_PISR 0x04 // Period Interval Status Register #define AT91_PITC_PISR_PITS (1 << 0) // Periodic Interval Timer Status #define AT91_PITC_PIVR 0x08 // Period Interval Status Register @@ -1167,7 +1620,7 @@ //============================================================================= // Real Time Timer Controller -#if defined(CYGHWR_HAL_ARM_AT91SAM7S) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) #ifndef AT91_RTTC #define AT91_RTTC 0xFFFFFD20 @@ -1187,7 +1640,7 @@ //============================================================================= // USB Device Port -#if defined(CYGHWR_HAL_ARM_AT91SAM7S) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) #ifndef AT91_UDP #define AT91_UDP 0xFFFB0000 @@ -1253,10 +1706,10 @@ //============================================================================= // Synchronous Serial Controller (SSC) -#if defined(CYGHWR_HAL_ARM_AT91SAM7S) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) #ifndef AT91_SSC - #define AT91_SSC 0xFFFD4000 +#define AT91_SSC 0xFFFD4000 #endif #define AT91_SSC_CR (0x00) @@ -1277,7 +1730,7 @@ #define AT91_SSC_RCMR_CKG_NONE (0<<6) //No Clock Gating, Continuous Clock #define AT91_SSC_RCMR_CKG_RFLOW (1<<6) //Clock Enabled by RF Low #define AT91_SSC_RCMR_CKG_RFHIGH (2<<6) //Clock Enabled by RF HIGH -#define AT91_SSC_RCMR_START_CONT (0<<8) //Start when data in RHR, Continous operation +#define AT91_SSC_RCMR_START_CONT (0<<8) //Start when data in RHR, Continuous #define AT91_SSC_RCMR_START_TX (1<<8) //Start when TX Start #define AT91_SSC_RCMR_START_RFLOW (2<<8) //Start when LOW level on RF #define AT91_SSC_RCMR_START_RFHIGH (3<<8) //Start when HIGH level on RF @@ -1293,16 +1746,16 @@ #define AT91_SSC_RFMR_DATLEN(x) (x&0x1F) //Data word length #define AT91_SSC_RFMR_LOOP (1<<5) //Loop Mode #define AT91_SSC_RFMR_MSBF (1<<7) //MSB First -#define AT91_SSC_RFMR_DATNB(x) ((x&0xf)<<8) //Data Number, Number of words per frame +#define AT91_SSC_RFMR_DATNB(x) ((x&0xf)<<8) //Data Number, # words per frame #define AT91_SSC_RFMR_FSLEN(x) ((x&0xf)<<16) //Frame sync length #define AT91_SSC_RFMR_FSOS_NONE (0<<16) //No Frame Synch Output -#define AT91_SSC_RFMR_FSOS_NEGPULSE (1<<16) //Negative Pulse Frame Synch Output -#define AT91_SSC_RFMR_FSOS_POSPULSE (2<<16) //Positive Pulse Frame Synch Output +#define AT91_SSC_RFMR_FSOS_NEGPULSE (1<<16) //Negative Pulse Frame Sync Output +#define AT91_SSC_RFMR_FSOS_POSPULSE (2<<16) //Positive Pulse Frame Sync Output #define AT91_SSC_RFMR_FSOS_LOW (3<<16) //Low Level Frame Synch Output #define AT91_SSC_RFMR_FSOS_HIGH (4<<16) //High Level Frame Synch Output #define AT91_SSC_RFMR_FSOS_TOGGLE (5<<16) //Toggle Frame Synch Output -#define AT91_SSC_RFMR_FSEDGE_POS (0<<24) //RXSYN interrupt on Postive edge of Frame Sync -#define AT91_SSC_RFMR_FSEDGE_NEG (1<<24) //RXSYN interrupt on Postive edge of Frame Sync +#define AT91_SSC_RFMR_FSEDGE_POS (0<<24) //Intr on +ve edge of Frame Sync +#define AT91_SSC_RFMR_FSEDGE_NEG (1<<24) //Intr on -ve edge of Frame Sync #define AT91_SSC_TCMR (0x18) #define AT91_SSC_TCMR_CKS_DIV (0<<0) //Select Divider Clock #define AT91_SSC_TCMR_CKS_TX (1<<0) //Select Transmit Clock @@ -1314,32 +1767,32 @@ #define AT91_SSC_TCMR_CKG_NONE (0<<6) //No Clock Gating, Continuous Clock #define AT91_SSC_TCMR_CKG_RFLOW (1<<6) //Clock Enabled by RF Low #define AT91_SSC_TCMR_CKG_RFHIGH (2<<6) //Clock Enabled by RF HIGH -#define AT91_SSC_TCMR_START_CONT (0<<8) //Start when data in THR, Continous operation -#define AT91_SSC_TCMR_START_TX (1<<8) //Start when TX Start -#define AT91_SSC_TCMR_START_RFLOW (2<<8) //Start when LOW level on RF -#define AT91_SSC_TCMR_START_RFHIGH (3<<8) //Start when HIGH level on RF -#define AT91_SSC_TCMR_START_RFFALL (4<<8) //Start when Falling Edge on RF -#define AT91_SSC_TCMR_START_RFRISE (5<<8) //Start when Rising Edge on RF -#define AT91_SSC_TCMR_START_RFLEVEL (6<<8) //Start when any Level Change on RF -#define AT91_SSC_TCMR_START_RFEDGE (6<<8) //Start when any Edge on RF +#define AT91_SSC_TCMR_START_CONT (0<<8) //Start when data in THR, Continuous +#define AT91_SSC_TCMR_START_TX (1<<8) //Start when TX Start +#define AT91_SSC_TCMR_START_RFLOW (2<<8) //Start when LOW level on RF +#define AT91_SSC_TCMR_START_RFHIGH (3<<8) //Start when HIGH level on RF +#define AT91_SSC_TCMR_START_RFFALL (4<<8) //Start when Falling Edge on RF +#define AT91_SSC_TCMR_START_RFRISE (5<<8) //Start when Rising Edge on RF +#define AT91_SSC_TCMR_START_RFLEVEL (6<<8) //Start when any Level Change on RF +#define AT91_SSC_TCMR_START_RFEDGE (6<<8) //Start when any Edge on RF #define AT91_SSC_TCMR_STDDLY(x) ((x&0xFF)<<16) //Start Delay #define AT91_SSC_TCMR_PERIOD(x) ((x&0xFF)<<24) //Frame Period #define AT91_SSC_TFMR (0x1C) #define AT91_SSC_TFMR_DATLEN(x) (x&0x1F) //Data word length #define AT91_SSC_TFMR_DATDEF (1<<5) //Default Data is 1's #define AT91_SSC_TFMR_MSBF (1<<7) //MSB First -#define AT91_SSC_TFMR_DATNB(x) ((x&0xf)<<8) //Data Number, Number of words per frame -#define AT91_SSC_TFMR_FSLEN(x) ((x&0xf)<<16) //Frame sync length -#define AT91_SSC_TFMR_FSOS_NONE (0<<16) //No Frame Synch Output -#define AT91_SSC_TFMR_FSOS_NEGPULSE (1<<16) //Negative Pulse Frame Synch Output -#define AT91_SSC_TFMR_FSOS_POSPULSE (2<<16) //Positive Pulse Frame Synch Output -#define AT91_SSC_TFMR_FSOS_LOW (3<<16) //Low Level Frame Synch Output -#define AT91_SSC_TFMR_FSOS_HIGH (4<<16) //High Level Frame Synch Output -#define AT91_SSC_TFMR_FSOS_TOGGLE (5<<16) //Toggle Frame Synch Output -#define AT91_SSC_RFMR_FSDEN_DEF (0<<23) //Frame Sync is Default Data -#define AT91_SSC_RFMR_FSDEN_TSHR (1<<23) //Frame Sync is TSHR Data -#define AT91_SSC_RFMR_FSEDGE_POS (0<<24) //TXSYN interrupt on Postive edge of Frame Sync -#define AT91_SSC_RFMR_FSEDGE_NEG (1<<24) //TXSYN interrupt on Postive edge of Frame Sync +#define AT91_SSC_TFMR_DATNB(x) ((x&0xf)<<8) //Data Number, # words per frame +#define AT91_SSC_TFMR_FSLEN(x) ((x&0xf)<<16) //Frame sync length +#define AT91_SSC_TFMR_FSOS_NONE (0<<16) //No Frame Synch Output +#define AT91_SSC_TFMR_FSOS_NEGPULSE (1<<16) //Negative Pulse Frame Sync Output +#define AT91_SSC_TFMR_FSOS_POSPULSE (2<<16) //Positive Pulse Frame Sync Output +#define AT91_SSC_TFMR_FSOS_LOW (3<<16) //Low Level Frame Synch Output +#define AT91_SSC_TFMR_FSOS_HIGH (4<<16) //High Level Frame Synch Output +#define AT91_SSC_TFMR_FSOS_TOGGLE (5<<16) //Toggle Frame Synch Output +#define AT91_SSC_RFMR_FSDEN_DEF (0<<23) //Frame Sync is Default Data +#define AT91_SSC_RFMR_FSDEN_TSHR (1<<23) //Frame Sync is TSHR Data +#define AT91_SSC_RFMR_FSEDGE_POS (0<<24) //Intr on +ve edge of Frame Sync +#define AT91_SSC_RFMR_FSEDGE_NEG (1<<24) //Intr on -ve edge of Frame Sync #define AT91_SSC_RHR (0x20) #define AT91_SSC_THR (0x24) #define AT91_SSC_RSHR (0x30) @@ -1384,9 +1837,647 @@ #endif //============================================================================= +// Ethernet Controller (EMAC) + +#if defined(CYGHWR_HAL_ARM_AT91SAM7X) + +#ifndef AT91_EMAC +#define AT91_EMAC 0xFFFBC000 +#endif + + +#define AT91_EMAC_CTL (0x00) // Network Control +#define AT91_EMAC_CTL_LB (1 << 0) // Loopback +#define AT91_EMAC_CTL_LBL (1 << 1) // Loopback Local +#define AT91_EMAC_CTL_RE (1 << 2) // Receiver Enable +#define AT91_EMAC_CTL_TX (1 << 3) // Transmit Enable +#define AT91_EMAC_CTL_MPE (1 << 4) // Management Port Enable +#define AT91_EMAC_CTL_CSR (1 << 5) // Clear Statistics Registers +#define AT91_EMAC_CTL_ISR (1 << 6) // Increment Statistics Registers +#define AT91_EMAC_CTL_WES (1 << 7) // Write Enable for Statistics Registers +#define AT91_EMAC_CTL_BP (1 << 8) // Back Pressure +#define AT91_EMAC_CTL_TSTART (1 << 9) // Start Transmitter +#define AT91_EMAC_CTL_THALT (1 << 10) // Halt Transmitter + +#define AT91_EMAC_CFG (0x04) // Network Configuration +#define AT91_EMAC_CFG_SPD_10Mbps (0 << 0) // 10Mbps line speed +#define AT91_EMAC_CFG_SPD_100Mbps (1 << 0) // 100Mbps line speed +#define AT91_EMAC_CFG_FD (1 << 1) // Full Deplex +#define AT91_EMAC_CFG_BR (1 << 2) // Bit Rate +#define AT91_EMAC_CFG_CAF (1 << 4) // Copy All Frames +#define AT91_EMAC_CFG_NBC (1 << 5) // Don't receiver Broadcasts +#define AT91_EMAC_CFG_MTI (1 << 6) // Multicast Hash Enable +#define AT91_EMAC_CFG_UNI (1 << 7) // Unicast hash enable +#define AT91_EMAC_CFG_BIG (1 << 8) // Receive upto 1522 byte frames +#define AT91_EMAC_CFG_EAE (1 << 9) // External Address match Enable +#define AT91_EMAC_CFG_CLK_HCLK_8 (0 << 10) // HCLK divided by 8 +#define AT91_EMAC_CFG_CLK_HCLK_16 (1 << 10) // HCLK divided by 16 +#define AT91_EMAC_CFG_CLK_HCLK_32 (2 << 10) // HCLK divided by 32 +#define AT91_EMAC_CFG_CLK_HCLK_64 (3 << 10) // HCLK divided by 64 +#define AT91_EMAC_CFG_CLK_MASK (3 << 10) // HCLK mask +#define AT91_EMAC_CFG_CLK_RTY (1 << 12) // Retry Test +#define AT91_EMAC_CFG_CLK_RMII (1 << 13) // Enable RMII mode +#define AT91_EMAC_CFG_CLK_MII (0 << 13) // Enable MII mode +#define AT91_EMAC_SR (0x08) // Network Status +#define AT91_EMAC_SR_MDIO_MASK (1 << 1) // MDIO Pin status +#define AT91_EMAC_SR_IDLE (1 << 2) // PHY logical is idle +#define AT91_EMAC_TAR (0x0c) // Transmit Address +#define AT91_EMAC_TCR (0x10) // Transmit Control +#define AT91_EMAC_TCR_LEN_MASK (0x3ff << 0) // Transmit frame length +#define AT91_EMAC_TCR_NCRC ( 1 << 15) // No CRC added by MAC +#define AT91_EMAC_TSR (0x14) // Transmit Status +#define AT91_EMAC_TSR_OVR (1 << 0) // Overrun +#define AT91_EMAC_TSR_COL (1 << 1) // Collision occurred +#define AT91_EMAC_TSR_RLE (1 << 2) // Retry Limit Exceeded +#define AT91_EMAC_TSR_TXIDLE (1 << 3) // Transmitter Idle +#define AT91_EMAC_TSR_BNQ (1 << 4) // Buffer Not Queues +#define AT91_EMAC_TSR_COMP (1 << 5) // Transmission Complete +#define AT91_EMAC_TSR_UND (1 << 6) // Transmit Underrun +#define AT91_EMAC_RBQP (0x18) // Receiver Buffer Queue Pointer +#define AT91_EMAC_TBQP (0x1c) // Transmit Buffer Queue Pointer +#define AT91_EMAC_RSR (0x20) // Receiver Status +#define AT91_EMAC_RSR_BNA (1 << 0) // Buffer Not Available +#define AT91_EMAC_RSR_REC (1 << 1) // Frame Received +#define AT91_EMAC_RSR_OVR (1 << 2) // Transmit Buffer Overrun +#define AT91_EMAC_ISR (0x24) // Interrupt Status +#define AT91_EMAC_ISR_DONE (1 << 0) // Management Done +#define AT91_EMAC_ISR_RCOM (1 << 1) // Receiver Complete +#define AT91_EMAC_ISR_RBNA (1 << 2) // Receiver Buffer Not Available +#define AT91_EMAC_ISR_TOVR (1 << 3) // Transmit Buffer Overrun +#define AT91_EMAC_ISR_TUND (1 << 4) // Transmit Error: Buffer under run +#define AT91_EMAC_ISR_RTRY (1 << 5) // Transmit Error: Retry Limit Exceeded +#define AT91_EMAC_ISR_TBRE (1 << 6) // Transmit Buffer Register Empty +#define AT91_EMAC_ISR_TCOM (1 << 7) // Transmit Complete +#define AT91_EMAC_ISR_TIDLE (1 << 8) // Transmitter Idle +#define AT91_EMAC_ISR_LINK (1 << 9) // Link pin changed state +#define AT91_EMAC_ISR_ROVR (1 << 10) // Receiver Overrun +#define AT91_EMAC_ISR_HRESP (1 << 11) // HRESP not OK +#define AT91_EMAC_IER (0x28) // Interrupt Enable +#define AT91_EMAC_IDR (0x2c) // Interrupt Disable +#define AT91_EMAC_IMR (0x30) // Interrupt Mask +#define AT91_EMAC_MAN (0x34) // PHY Maintenance +#define AT91_EMAC_MAN_DATA_MASK (0xffff << 0) // Data to/from PHY +#define AT91_EMAC_MAN_CODE (2 << 16) // Code +#define AT91_EMAC_MAN_REGA_MASK (0x1f << 18) // Register Address Mask +#define AT91_EMAC_MAN_REGA_SHIFT (18) // Register Address Shift +#define AT91_EMAC_MAN_PHY_MASK (0x1f << 23) // PHY Address Mask +#define AT91_EMAC_MAN_PHY_SHIFT (23) // PHY Address Shift +#define AT91_EMAC_MAN_RD (2 << 28) // Read operation +#define AT91_EMAC_MAN_WR (1 << 28) // Write Operation +#define AT91_EMAC_MAN_HIGH (1 << 30) // Must be set to 1 +#define AT91_EMAC_FRA (0x40) // Frames Transmitted OK +#define AT91_EMAC_SCOL (0x44) // Single Collision Frame +#define AT91_EMAC_MCOL (0x48) // Multiple Collision Frame +#define AT91_EMAC_OK (0x4c) // Frames Received OK +#define AT91_EMAC_SEQE (0x50) // Frame Check Sequence Error +#define AT91_EMAC_ALE (0x54) // Alignment Error +#define AT91_EMAC_DTR (0x58) // Deferred Transmission Frame +#define AT91_EMAC_LCOL (0x5c) // Late Collision +#define AT91_EMAC_XCOL (0x60) // Excessive Collisions - ECAL!! +#define AT91_EMAC_CSE (0x64) // Carrier Sense Error +#define AT91_EMAC_TUE (0x68) // Transmit Underrun Error +#define AT91_EMAC_CDE (0x6c) // Code Error +#define AT91_EMAC_ELR (0x70) // Excessive Length +#define AT91_EMAC_RJB (0x74) // Receiver Jabber +#define AT91_EMAC_USF (0x78) // Undersize Frame +#define AT91_EMAC_SQEE (0x7c) // SEQ Test Error +#define AT91_EMAC_DRFC (0x80) // Discarded RX Frame +#define AT91_EMAC_HSH (0x90) // Hash Address High [63:21] +#define AT91_EMAC_HSL (0x94) // Hash Address Low [31:0] +#define AT91_EMAC_SA1L (0x98) // Specific Address 1 Low, First 4 bytes +#define AT91_EMAC_SA1H (0x9c) // Specific Address 1 High, Last 2 bytes +#define AT91_EMAC_SA2L (0xa0) // Specific Address 2 Low, First 4 bytes +#define AT91_EMAC_SA2H (0xa4) // Specific Address 2 High, Last 2 bytes +#define AT91_EMAC_SA3L (0xa8) // Specific Address 3 Low, First 4 bytes +#define AT91_EMAC_SA3H (0xac) // Specific Address 3 High, Last 2 bytes +#define AT91_EMAC_SA4L (0xb0) // Specific Address 4 Low, First 4 bytes +#define AT91_EMAC_SA4H (0xb4) // Specific Address 4 High, Last 2 bytes + +// Receiver Buffer Descriptor +#define AT91_EMAC_RBD_ADDR 0x0 // Address to beginning of buffer +#define AT91_EMAC_RBD_ADDR_OWNER_EMAC (0 << 0) // EMAC owns receiver buffer +#define AT91_EMAC_RBD_ADDR_OWNER_SW (1 << 0) // SW owns receiver buffer +#define AT91_EMAC_RBD_ADDR_WRAP (1 << 1) // Last receiver buffer +#define AT91_EMAC_RBD_SR 0x1 // Buffer Status +#define AT91_EMAC_RBD_SR_LEN_MASK (0xfff) // Length of data +#define AT91_EMAC_RBD_SR_SOF (1 << 14) // Start of Frame +#define AT91_EMAC_RBD_SR_EOF (1 << 15) // End of Frame +#define AT91_EMAC_RBD_SR_CFI (1 << 16) // Concatination Format Ind +#define AT91_EMAC_RDB_SR_VLAN_SHIFT (17) // VLAN priority tag +#define AT91_EMAC_RDB_SR_VLAN_MASK (7 << 17) +#define AT91_EMAC_RDB_SR_PRIORTY_TAG (1 << 20) // Priority Tag Detected +#define AT91_EMAC_RDB_SR_VLAN_TAG (1 << 21) // Priority Tag Detected +#define AT91_EMAC_RBD_SR_TYPE_ID (1 << 22) // Type ID match +#define AT91_EMAC_RBD_SR_SA4M (1 << 23) // Specific Address 4 match +#define AT91_EMAC_RBD_SR_SA3M (1 << 24) // Specific Address 3 match +#define AT91_EMAC_RBD_SR_SA2M (1 << 25) // Specific Address 2 match +#define AT91_EMAC_RBD_SR_SA1M (1 << 26) // Specific Address 1 match +#define AT91_EMAC_RBD_SR_EXTNM (1 << 28) // External Address match +#define AT91_EMAC_RBD_SR_UNICAST (1 << 29) // Unicast hash match +#define AT91_EMAC_RBD_SR_MULTICAST (1 << 30) // Multicast hash match +#define AT91_EMAC_RBD_SR_BROADCAST (1 << 31) // Broadcast + +// Transmit Buffer Descriptor +#define AT91_EMAC_TBD_ADDR 0x0 // Address to beginning of buffer +#define AT91_EMAC_TBD_SR 0x1 // Buffer Status +#define AT91_EMAC_TBD_SR_LEN_MASK (0xfff) // Length of data +#define AT91_EMAC_TBD_SR_EOF (1 << 15) // End of Frame +#define AT91_EMAC_TBD_SR_NCRC (1 << 16) // No CRC added by EMAC +#define AT91_EMAC_TBD_SR_EXHAUST (1 << 27) // Buffers exhausted +#define AT91_EMAC_TBD_SR_TXUNDER (1 << 28) // Transmit Underrun +#define AT91_EMAC_TBD_SR_RTRY (1 << 29) // Retry limit exceeded +#define AT91_EMAC_TBD_SR_WRAP (1 << 30) // Marks last descriptor +#define AT91_EMAC_TBD_SR_USED (1 << 31) // Buffer used + +#endif + +//============================================================================= +// Two Wire Interface (TWI) + +#if defined(CYGHWR_HAL_ARM_AT91SAM7) + +#ifndef AT91_TWI +#define AT91_TWI 0xFFFB8000 +#endif + +#define AT91_TWI_CR 0x00 // Control +#define AT91_TWI_CR_START (1 << 0) // Send a Start +#define AT91_TWI_CR_STOP (1 << 1) // Send a Stop +#define AT91_TWI_CR_MSEN (1 << 2) // Master Transfer Enable +#define AT91_TWI_CR_MSDIS (1 << 3) // Master Transfer Disable +#define AT91_TWI_CR_SVEN (1 << 4) // Slave Transfer Enable +#define AT91_TWI_CR_SDIS (1 << 5) // Slave Transfer Disable +#define AT91_TWI_CR_SWRST (1 << 7) // Software Reset +#define AT91_TWI_MMR 0x04 // Master Mode +#define AT91_TWI_MMR_IADRZ_NO (0 << 8) // Internal Device Address size 0Bytes +#define AT91_TWI_MMR_IADRZ_1 (1 << 8) // Internal Device Address size 1Byte +#define AT91_TWI_MMR_IADRZ_2 (2 << 8) // Internal Device Address size 2Bytes +#define AT91_TWI_MMR_IADRZ_3 (3 << 8) // Internal Device Address size 3Bytes +#define AT91_TWI_MMR_MWRITE (0 << 12) // Master Write +#define AT91_TWI_MMR_MREAD (1 << 12) // Master Read +#define AT91_TWI_MMR_DADR_MASK (0x3f << 16) // Device Address Mask +#define AT91_TWI_MMR_DADR_SHIFT (16) // Device Address Shift +#define AT91_TWI_SMR 0x08 // Slave Mode +#define AT91_TWI_SMR_SADR_MASK (0x3f << 16) // Slave Device Address Mask +#define AT91_TWI_SMR_SADR_SHIFT (16) // Slave Device Address Shift +#define AT91_TWI_IADR 0x0C // Internal Address +#define AT91_TWI_CWGR 0x10 // Clock Waveform Generator +#define AT91_TWI_CWGR_CLDIV_MASK (0xf << 0) // Clock Low Divider Mask +#define AT91_TWI_CWGR_CLDIV_SHIFT (00) // Clock Low Divider Shift +#define AT91_TWI_CWGR_CHDIV_MASK (0xf << 8) // Clock High Divider Mask +#define AT91_TWI_CWGR_CHDIV_SHIFT (08) // Clock High Divider Shift +#define AT91_TWI_CWGR_CKDIV_MASK (0x7 << 16) // Clock Divider Mask +#define AT91_TWI_CWGR_CKDIV_SHIFT (16) // Clock Divider Shift +#define AT91_TWI_SR 0x20 // Status +#define AT91_TWI_SR_TXCOMP (1 << 0) // Transmission Completed +#define AT91_TWI_SR_RXRDY (1 << 1) // Receiver Holding Register Ready +#define AT91_TWI_SR_TXRDY (1 << 2) // Transmit Holding Register Ready +#define AT91_TWI_SR_SVREAD (1 << 3) // Slave Read +#define AT91_TWI_SR_SVACC (1 << 4) // Slave Access +#define AT91_TWI_SR_GCACC (1 << 5) // General Call Access +#define AT91_TWI_SR_OVRE (1 << 6) // Overrun Error +#define AT91_TWI_SR_UNRE (1 << 7) // Underrun Error +#define AT91_TWI_SR_NACK (1 << 8) // Not Acknowledged +#define AT91_TWI_SR_ARBLST (1 << 9) // Arbitration Lost +#define AT91_TWI_IER 0x24 // Interrupt Enable +#define AT91_TWI_IDR 0x28 // Interrupt Disable +#define AT91_TWI_IMR 0x2C // Interrupt Mask +#define AT91_TWI_RHR 0x30 // Receiver Holding +#define AT91_TWI_THR 0x34 // Transmit Holding +#endif + +//============================================================================= +// Analog to Digital Convertor (ADC) + +#if defined(CYGHWR_HAL_ARM_AT91SAM7) + +#ifndef AT91_ADC +#define AT91_ADC 0xFFFD8000 +#endif + +#define AT91_ADC_CR 0x00 // Control +#define AT91_ADC_CR_SWRST (1 << 0) // Software Reset +#define AT91_ADC_CR_START (1 << 1) // Start Conversion +#define AT91_ADC_MR 0x04 // Mode +#define AT91_ADC_MR_TRGSEL_TIOA0 (0 << 1) // Trigger = TIAO0 +#define AT91_ADC_MR_TRGSEL_TIOA1 (1 << 1) // Trigger = TIAO1 +#define AT91_ADC_MR_TRGSEL_TIOA2 (2 << 1) // Trigger = TIAO2 +#define AT91_ADC_MR_TRGSEL_TIOA3 (3 << 1) // Trigger = TIAO3 +#define AT91_ADC_MR_TRGSEL_TIOA4 (4 << 1) // Trigger = TIAO4 +#define AT91_ADC_MR_TRGSEL_TIOA5 (5 << 1) // Trigger = TIAO5 +#define AT91_ADC_MR_TRGSEL_EXT (6 << 1) // Trigger = External +#define AT91_ADC_MR_LOWREC_10BITS (0 << 4) // 10-bit Resolution +#define AT91_ADC_MR_LOWRES_8BITS (1 << 4) // 8-bit resolution +#define AT91_ADC_MR_SLEEP_ON (1 << 5) // Sleep mode on +#define AT91_ADC_MR_SLEEP_OFF (0 << 5) // Sleep mode off +#define AT91_ADC_MR_PRESCAL_MASK (0x3f << 8) // Prescale Mask +#define AT91_ADC_MR_PRESCAL_SHIFT (8) // Prescale Shift +#define AT91_ADC_MR_STARTUP_MASK (0x0f << 16) // Startup Time Mask +#define AT91_ADC_MR_STARTUP_SHIFT (16) // Startup Time Mask +#define AT91_ADC_MR_SHTIM_MASK (0x0f << 24) // Sample & Hold Time Mask +#define AT91_ADC_MR_SHTIM_SHIFT (24) // Sample & Hold Time Shift +#define AT91_ADC_CHER 0x10 // Channel Enable +#define AT91_ADC_CHER_CH0 (1 << 0) // Channel 0 +#define AT91_ADC_CHER_CH1 (1 << 1) // Channel 1 +#define AT91_ADC_CHER_CH2 (1 << 2) // Channel 2 +#define AT91_ADC_CHER_CH3 (1 << 3) // Channel 3 +#define AT91_ADC_CHER_CH4 (1 << 4) // Channel 4 +#define AT91_ADC_CHER_CH5 (1 << 5) // Channel 5 +#define AT91_ADC_CHER_CH6 (1 << 6) // Channel 6 +#define AT91_ADC_CHER_CH7 (1 << 7) // Channel 7 +#define AT91_ADC_CHDR 0x14 // Channel Disable +#define AT91_ADC_CHSR 0x18 // Channel Status +#define AT91_ADC_SR 0x1c // Status +#define AT91_ADC_CHSR_EOC0 (1 << 0) // Channel 0 End of Conversion +#define AT91_ADC_CHSR_EOC1 (1 << 1) // Channel 1 End of Conversion +#define AT91_ADC_CHSR_EOC2 (1 << 2) // Channel 2 End of Conversion +#define AT91_ADC_CHSR_EOC3 (1 << 3) // Channel 3 End of Conversion +#define AT91_ADC_CHSR_EOC4 (1 << 4) // Channel 4 End of Conversion +#define AT91_ADC_CHSR_EOC5 (1 << 5) // Channel 5 End of Conversion +#define AT91_ADC_CHSR_EOC6 (1 << 6) // Channel 6 End of Conversion +#define AT91_ADC_CHSR_EOC7 (1 << 7) // Channel 7 End of Conversion +#define AT91_ADC_CHSR_OVRE0 (1 << 8) // Channel 0 Overrun Error +#define AT91_ADC_CHSR_OVRE1 (1 << 9) // Channel 1 Overrun Error +#define AT91_ADC_CHSR_OVRE2 (1 << 10) // Channel 2 Overrun Error +#define AT91_ADC_CHSR_OVRE3 (1 << 11) // Channel 3 Overrun Error +#define AT91_ADC_CHSR_OVRE4 (1 << 12) // Channel 4 Overrun Error +#define AT91_ADC_CHSR_OVRE5 (1 << 13) // Channel 5 Overrun Error +#define AT91_ADC_CHSR_OVRE6 (1 << 14) // Channel 6 Overrun Error +#define AT91_ADC_CHSR_OVRE7 (1 << 15) // Channel 7 Overrun Error +#define AT91_ADC_CHSR_DRDY (1 << 16) // Data Ready +#define AT91_ADC_CHSR_GOVER (1 << 17) // General Overrun +#define AT91_ADC_CHSR_EDNRX (1 << 18) // End of Receiver Transfer +#define AT91_ADC_CHSR_RXBUFF (1 << 19) // RXBUFFER Interrupt +#define AT91_ADC_LCDR 0x20 // Last Converted Data +#define AT91_ADC_IER 0x24 // Interrupt Enable +#define AT91_ADC_IDR 0x28 // Interrupt Disable +#define AT91_ADC_IMR 0x2c // Interrupt Mask +#define AT91_ADC_CDR0 0x30 // Channel Data 0 +#define AT91_ADC_CDR1 0x34 // Channel Data 1 +#define AT91_ADC_CDR2 0x38 // Channel Data 2 +#define AT91_ADC_CDR3 0x3c // Channel Data 3 +#define AT91_ADC_CDR4 0x40 // Channel Data 4 +#define AT91_ADC_CDR5 0x44 // Channel Data 5 +#define AT91_ADC_CDR6 0x48 // Channel Data 6 +#define AT91_ADC_CDR7 0x4c // Channel Data 7 +#define AT91_ADC_RPR 0x100 // Receive Pointer +#define AT91_ADC_RCR 0x104 // Receive Counter +#define AT91_ADC_TPR 0x108 // Transmit Pointer +#define AT91_ADC_TCR 0x10C // Transmit Counter +#define AT91_ADC_RNPR 0x110 // Receive Next Pointer +#define AT91_ADC_RNCR 0x114 // Receive Next Counter +#define AT91_ADC_TNPR 0x118 // Transmit Next Pointer +#define AT91_ADC_TNCR 0x11C // Transmit Next Counter +#define AT91_ADC_PTCR 0x120 // PDC Transfer Control +#define AT91_ADC_PTSR 0x124 // PDC Transfer Status + +#endif + +//============================================================================= +// Controller Area Network (CAN) + +#if defined(CYGHWR_HAL_ARM_AT91SAM7X) + +#ifndef AT91_CAN +#define AT91_CAN 0xFFFD8000 +#endif + +#define AT91_CAN_MR 0x000 // Mode +#define AT91_CAN_MR_CANEN (1 << 0) // Enable +#define AT91_CAN_MR_LPM (1 << 1) // Enable Low Power Mode +#define AT91_CAN_MR_ABM (1 << 2) // Enable Autobaud/Listen mode +#define AT91_CAN_MR_OVL (1 << 3) // Enable Overload Frame +#define AT91_CAN_MR_TEOF (1 << 4) // Timestamp at End Of Trame +#define AT91_CAN_MR_TTM (1 << 5) // Enable Time Triggered Mode +#define AT91_CAN_MR_TIMFRZ (1 << 6) // Enable Timer Freeze +#define AT91_CAN_MR_DRPT (1 << 7) // Disable Repeat +#define AT91_CAN_IER 0x004 // Interrupt Enable +#define AT91_CAM_IER_MB0 (1 << 0) // Mailbox 0 +#define AT91_CAM_IER_MB1 (1 << 1) // Mailbox 1 +#define AT91_CAM_IER_MB2 (1 << 2) // Mailbox 2 +#define AT91_CAM_IER_MB3 (1 << 3) // Mailbox 3 +#define AT91_CAM_IER_MB4 (1 << 4) // Mailbox 4 +#define AT91_CAM_IER_MB5 (1 << 5) // Mailbox 5 +#define AT91_CAM_IER_MB6 (1 << 6) // Mailbox 6 +#define AT91_CAM_IER_MB7 (1 << 7) // Mailbox 7 +#define AT91_CAM_IER_ERRA (1 << 16) // Error Active Mode +#define AT91_CAM_IER_WARN (1 << 17) // Warning Limit +#define AT91_CAM_IER_ERRO (1 << 18) // Error Passive Mode +#define AT91_CAM_IER_BOFF (1 << 19) // Bus-Off Mode +#define AT91_CAM_IER_SLEEP (1 << 20) // Sleep +#define AT91_CAM_IER_WAKEUP (1 << 21) // Wakeup +#define AT91_CAM_IER_TOVF (1 << 22) // Timer Overflow +#define AT91_CAM_IER_TSTP (1 << 23) // TimeStamp +#define AT91_CAM_IER_CERR (1 << 24) // CRC Error +#define AT91_CAM_IER_SERR (1 << 25) // Stuffing Error +#define AT91_CAM_IER_AERR (1 << 26) // Acknowledgement Error +#define AT91_CAM_IER_FERR (1 << 27) // Form Error +#define AT91_CAM_IER_BERR (1 << 28) // Bit Error +#define AT91_CAN_IDR 0x008 // Interrupt Disable +#define AT91_CAN_IMR 0x00C // Interrupt Mask +#define AT91_CAN_SR 0x010 // Status +#define AT91_CAN_SR_RBSY (1 << 29) // Receiver busy +#define AT91_CAM_SR_TBSY (1 << 30) // Transmitter busy +#define AT91_CAM_IER_OVLSY (1 << 31) // Overload Busy +#define AT91_CAN_BR 0x014 // Baudrate +#define AT91_CAN_BR_PHASE1_MASK (0x7 << 4) // Phase 1 Segment mask +#define AT91_CAN_BR_PHASE1_SHIFT (4) // Phase 1 Segment shift +#define AT91_CAN_BR_PHASE2_MASK (0x7 << 0) // Phase 2 Segment mask +#define AT91_CAN_BR_PHASE2_SHIFT (0) // Phase 2 Segment shift +#define AT91_CAN_BR_PROPAG_MASK (0x7 << 8) // Programming Time Segment mask +#define AT91_CAN_BR_PROPAG_SHIFT (8) // Programming Time Segment shift +#define AT91_CAN_BR_SJW_MASK (0x3 << 12) // Re-Sync jump width mask +#define AT91_CAN_BR_SJW_SHIFT (12) // Re-Sync jump width shift +#define AT91_CAN_BR_BRP_MASK (0x7f << 16) // Baudrate Prescaler mask +#define AT91_CAN_BR_BRP_SHIFT (16) // Baudrate Prescaler mask +#define AT91_CAN_BR_SMP_ONCE (0 << 24) // Sampling once +#define AT91_CAN_BR_SMP_THRICE (1 << 24) // Sampling three times +#define AT91_CAN_TIM 0x018 // Timer +#define AT91_CAN_TIMESTP 0x01c // Timestamp +#define AT91_CAN_ECR 0x020 // Error Counter +#define AT91_CAN_ECR_REC_MASK (0xf << 0) // Receiver Error Counter mask +#define AT91_CAN_ECR_REC_SHIFT (00) // Receiver Error Counter shift +#define AT91_CAN_ECR_TEC_MASK (0xf << 16) // Transmit Error Counter mask +#define AT91_CAN_ECR_TEC_SHIFT (00) // Transmit Error Counter shift +#define AT91_CAN_TCR 0x024 // Transfer Command +#define AT91_CAN_TCR_TIMRST (1 << 31) // Timer Reset +#define AT91_CAN_ACR 0x028 // Abort Command +#define AT91_CAN_MMR0 0x200 // Mailbox 0 Mode +#define AT91_CAN_MMR_PRIOR_MASK (0xf << 16) // Priority Mask +#define AT91_CAN_MMR_PRIOR_SHIFT (16) // Priority Shift +#define AT91_CAN_MMR_MOT_DISABLED (0 << 24) // Mailbox disabled +#define AT91_CAN_MMR_MOT_RECEPTION (1 << 24) // Reception Mailbox +#define AT91_CAN_MMR_MOT_RECEPTION_OVER (2 << 24) // Reception with Overwrite +#define AT91_CAM_MMR_MOT_TRANSMIT (3 << 24) // Transmit Mailbox +#define AT91_CAM_MMR_MOT_CONSUMER (4 << 24) // Transmit Mailbox +#define AT91_CAM_MMR_MOT_PRODUCER (5 << 24) // Transmit Mailbox +#define AT91_CAN_MAM0 0x204 // Mailbox 0 Acceptance Mask +#define AT91_CAM_MAM_MIDvB_MASK (0x3ffff << 0) // MIDvB mask +#define AT91_CAM_MAM_MIDvB_SHIFT (0) // MIDvB shift +#define AT91_CAM_MAM_MIDvA_MASK (0x7ff << 18) // MIDvB mask +#define AT91_CAM_MAM_MIDvA_SHIFT (18) // MIDvB shift +#define AT91_CAM_MAM_MIDE (1 << 29) // Identifier Version +#define AT91_CAN_MID0 0x208 // Mailbox 0 ID +#define AT91_CAN_MFID0 0x20C // Mailbox 0 Family ID +#define AT91_CAN_MSR0 0x210 // Mailbox 0 Status +#define AT91_CAM_MSR_MDLC_MASK (0xf << 16) // Mailbox Data Length Code mask +#define AT91_CAM_MSR_MDLC_SHIFT (16) // Mailbox Data Length Code shift +#define AT91_CAM_MSR_MRTR (1 << 20) // Mailbox Remote Tx Request +#define AT91_CAM_MSR_MABT (1 << 22) // Mailbox Abort +#define AT91_CAM_MSR_MRDY (1 << 23) // Mailbox Ready +#define AT91_CAM_MSR_MMI (1 << 24) // Mailbox Message Ignored +#define AT91_CAN_MDL0 0x214 // Mailbox 0 Data Low +#define AT91_CAN_MDH0 0x218 // Mailbox 0 Data High +#define AT91_CAN_MCR0 0x21c // Mailbox 0 Control +#define AT91_CAM_MCR_MDLC_MASK (0xf << 16) // Mailbox Data Length Code mask +#define AT91_CAM_MCR_MDLC_SHIFT (16) // Mailbox Data Length Code shift +#define AT91_CAM_MCR_MRTR (1 << 20) // Mailbox Remote Tx Request +#define AT91_CAM_MCR_MACR (1 << 22) // Mailbox Abort Request +#define AT91_CAM_MCR_MTCR (1 << 23) // Mailbox Transfer Command +#define AT91_CAN_MMR1 0x220 // Mailbox 1 Mode +#define AT91_CAN_MAM1 0x224 // Mailbox 1 Acceptance Mask +#define AT91_CAN_MID1 0x228 // Mailbox 1 ID +#define AT91_CAN_MFID1 0x22C // Mailbox 1 Family ID +#define AT91_CAN_MSR1 0x230 // Mailbox 1 Status +#define AT91_CAN_MDL1 0x234 // Mailbox 1 Data Low +#define AT91_CAN_MDH1 0x238 // Mailbox 1 Data High +#define AT91_CAN_MCR1 0x23c // Mailbox 1 Control + +#endif + + +//============================================================================= // FIQ interrupt vector which is shared by all HAL varients. #define CYGNUM_HAL_INTERRUPT_FIQ 0 + +// Macros for access the GPIO lines and configuring peripheral pins + +// Given a pin description, determine which PIO controller it is on +#define HAL_ARM_AT91_PIO_CTRL(_pin_) \ + ((_pin_ >> 16) & 0xff) + +// Given a pin description, determine which PIO bit controls this pin +#define HAL_ARM_AT91_PIO_BIT(_pin_) \ + (1 << (_pin_ & 0xff)) + +// Evaluate to true if the pin is using peripheral A +#define HAL_ARM_AT91_PIO_A(_pin_) \ + (((_pin_ >> 8) & 0xff) == 0) + +// Configure a peripheral pin on a specific PIO controller. +#ifdef AT91_PIO_ASR +#define HAL_ARM_AT91_PIOX_CFG(_pin_, _nr_, _pio_base_) \ + CYG_MACRO_START \ + if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PDR, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + if (HAL_ARM_AT91_PIO_A(_pin_)) { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_ASR, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } else { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_BSR, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } \ + } \ + CYG_MACRO_END +#else // AT91_PIO_ASR +#define HAL_ARM_AT91_PIOX_CFG(_pin_, _nr_, _pio_base_) \ + CYG_MACRO_START \ + if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PDR, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } \ + CYG_MACRO_END +#endif // !AT91_PIO_ASR + +// Configure a GPIO pin direction on a specific PIO controller. +#define HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, _nr_, _pio_base_) \ + CYG_MACRO_START \ + if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PER, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + if ((_dir_) == AT91_PIN_IN) { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_ODR, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } else { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_OER, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } \ + } \ + CYG_MACRO_END + +// Configure a GPIO pin pullup on a specific PIO controller. +#define HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, _nr_, _pio_base_) \ + CYG_MACRO_START \ + if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \ + if (_enable_) { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PPUER, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } else { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PPUDR, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } \ + } \ + CYG_MACRO_END + +// Set a GPIO pin on a specific PIO controller to generate interrupts +#define HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, _nr_, _pio_base_) \ + CYG_MACRO_START \ + if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \ + if (_enable_) { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_IER, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } else { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_IDR, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } \ + } \ + CYG_MACRO_END + +// Set a GPIO pin on a specific PIO controller. +#define HAL_ARM_AT91_GPIOX_SET(_pin_, _nr_, _pio_base_) \ + CYG_MACRO_START \ + if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_SODR, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } \ + CYG_MACRO_END + +// Reset a GPIO pin on a specific PIO controller. +#define HAL_ARM_AT91_GPIOX_RESET(_pin_, _nr_, _pio_base_) \ + CYG_MACRO_START \ + if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \ + HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_CODR, \ + HAL_ARM_AT91_PIO_BIT(_pin_)); \ + } \ + CYG_MACRO_END + +// Get a GPIO pin on a specific PIO controller. +#define HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, _nr_, _pio_base_) \ + CYG_MACRO_START \ + cyg_uint32 _pdsr_; \ + if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \ + HAL_READ_UINT32((_pio_base_)+AT91_PIO_PDSR, _pdsr_); \ + (_value_) = (_pdsr_ & HAL_ARM_AT91_PIO_BIT(_pin_) ? 1 : 0); \ + } \ + CYG_MACRO_END + +#define AT91_PIN_IN 1 +#define AT91_PIN_OUT 0 +#define AT91_PIN_PULLUP_ENABLE 1 +#define AT91_PIN_PULLUP_DISABLE 0 +#define AT91_PIN_INTERRUPT_ENABLE 1 +#define AT91_PIN_INTERRUPT_DISABLE 0 + +#ifndef AT91_PIOB +// Only one PIO controller + +// Configure a peripheral pin for peripheral operation +#define HAL_ARM_AT91_PIO_CFG(_pin_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \ + CYG_MACRO_END + +// Configure a GPIO pin direction +#define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \ + CYG_MACRO_END + +// Configure a GPIO pin pullup resistor +#define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \ + CYG_MACRO_END + +// Configure a GPIO pin to generate interrupts +#define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \ + CYG_MACRO_END + +// Configure a GPIO pin to generate interrupts +#define HAL_ARM_AT91_GPIO_SET(_pin_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \ + CYG_MACRO_END + +// Configure a GPIO pin to generate interrupts +#define HAL_ARM_AT91_GPIO_RESET(_pin_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \ + CYG_MACRO_END + +// Configure a GPIO pin to generate interrupts +#define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \ + CYG_MACRO_END + +#else // !AT91_PIOB +// Two PIO controllers + +// Configure a peripheral pin for peripheral operation +#define HAL_ARM_AT91_PIO_CFG(_pin_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \ + HAL_ARM_AT91_PIOX_CFG(_pin_, 1, AT91_PIOB); \ +CYG_MACRO_END + +// Configure a GPIO pin direction +#define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \ + HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 1, AT91_PIOB); \ + CYG_MACRO_END + +// Configure a GPIO pin pullup resistor +#define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \ + HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 1, AT91_PIOB); \ + CYG_MACRO_END + +// Configure a GPIO pin to generate interrupts +#define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \ + HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 1, AT91_PIOB); \ + CYG_MACRO_END + +// Set a GPIO pin to 1 +#define HAL_ARM_AT91_GPIO_SET(_pin_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \ + HAL_ARM_AT91_GPIOX_SET(_pin_, 1, AT91_PIOB); \ + CYG_MACRO_END + +// Reset a GPIO pin to 0 +#define HAL_ARM_AT91_GPIO_RESET(_pin_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \ + HAL_ARM_AT91_GPIOX_RESET(_pin_, 1, AT91_PIOB); \ + CYG_MACRO_END + +// Configure a GPIO pin to generate interrupts +#define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \ + CYG_MACRO_START \ + HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \ + HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 1, AT91_PIOB); \ + CYG_MACRO_END +#endif //!AT91_PIOB + +// Put a GPIO pin to a given state +#define HAL_ARM_AT91_GPIO_PUT(_pin_, _state_) \ + CYG_MACRO_START \ + if (_state_) { \ + HAL_ARM_AT91_GPIO_SET(_pin_); \ + } else { \ + HAL_ARM_AT91_GPIO_RESET(_pin_); \ + } \ + CYG_MACRO_END + //----------------------------------------------------------------------------- // end of var_io.h #endif // CYGONCE_HAL_VAR_IO_H Index: hal/arm/at91/at91sam7sek/current/ChangeLog =================================================================== RCS file: hal/arm/at91/at91sam7sek/current/ChangeLog diff -N hal/arm/at91/at91sam7sek/current/ChangeLog --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ hal/arm/at91/at91sam7sek/current/ChangeLog 2 Jun 2006 18:19:07 -0000 @@ -0,0 +1,35 @@ +2006-05-20 Andrew Lunn + + * AT91SAM7X-EK development board package + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2006 Andrew Lunn +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== Index: hal/arm/at91/at91sam7sek/current/cdl/hal_arm_at91sam7sek.cdl =================================================================== RCS file: hal/arm/at91/at91sam7sek/current/cdl/hal_arm_at91sam7sek.cdl diff -N hal/arm/at91/at91sam7sek/current/cdl/hal_arm_at91sam7sek.cdl --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ hal/arm/at91/at91sam7sek/current/cdl/hal_arm_at91sam7sek.cdl 2 Jun 2006 18:19:08 -0000 @@ -0,0 +1,64 @@ +# ==================================================================== +# +# hal_arm_at91_sam7sek.cdl +# +# ARM AT91 SAM7S EK development board package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## Copyright (C) 2006 Andrew Lunn +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): andrew lunn +# Contributors: +# Date: 2006-05-20 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_AT91SAM7SEK { + display "Atmel AT91SAM7S EK development board" + parent CYGPKG_HAL_ARM_AT91SAM7 + define_header hal_arm_at91sam7sek.h + include_dir cyg/hal + hardware + description " + The AT91SAM7SEK HAL package provides the support needed to run + eCos on an Atmel AT91SAM7S-EK development board." + + compile at91sam7sek_misc.c + + requires { CYGHWR_HAL_ARM_AT91 == "AT91SAM7S" } + requires { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s256" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s128" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s64" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s32" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s321" } +} Index: hal/arm/at91/at91sam7sek/current/src/at91sam7sek_misc.c =================================================================== RCS file: hal/arm/at91/at91sam7sek/current/src/at91sam7sek_misc.c diff -N hal/arm/at91/at91sam7sek/current/src/at91sam7sek_misc.c --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ hal/arm/at91/at91sam7sek/current/src/at91sam7sek_misc.c 2 Jun 2006 18:19:08 -0000 @@ -0,0 +1,77 @@ +/*========================================================================== +// +// at91sam7sek_misc.c +// +// HAL misc board support code for Atmel AT91sam7s EK board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2006 Andrew Lunn +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): andrew lunn +// Contributors: Oliver Munz, Andrew Lunn +// Date: 2006-06-20 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include +#include + +#include // IO macros + +// The development board has four LEDs +void +hal_at91_led (int val) +{ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PA0, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PA1, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PA2, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PA3, AT91_PIN_OUT); + + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PA0, AT91_PIN_PULLUP_DISABLE); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PA1, AT91_PIN_PULLUP_DISABLE); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PA2, AT91_PIN_PULLUP_DISABLE); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PA3, AT91_PIN_PULLUP_DISABLE); + + // Set the bits. The logic is inverted + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PA1, !(val & 1)); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PA2, !(val & 2)); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PA3, !(val & 4)); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PA4, !(val & 8)); +} + +//-------------------------------------------------------------------------- +// EOF at91sam7sek_misc.c Index: hal/arm/at91/at91sam7xek/current/ChangeLog =================================================================== RCS file: hal/arm/at91/at91sam7xek/current/ChangeLog diff -N hal/arm/at91/at91sam7xek/current/ChangeLog --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ hal/arm/at91/at91sam7xek/current/ChangeLog 2 Jun 2006 18:19:08 -0000 @@ -0,0 +1,35 @@ +2006-05-20 Andrew Lunn + + * AT91SAM7X-EK development board package + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2006 Andrew Lunn +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== Index: hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl =================================================================== RCS file: hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl diff -N hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ hal/arm/at91/at91sam7xek/current/cdl/hal_arm_at91sam7xek.cdl 2 Jun 2006 18:19:08 -0000 @@ -0,0 +1,61 @@ +# ==================================================================== +# +# hal_arm_at91_sam7xek.cdl +# +# ARM AT91 SAM7X EK development board package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## Copyright (C) 2006 Andrew Lunn +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): andrew lunn +# Contributors: +# Date: 2006-05-20 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_AT91SAM7XEK { + display "Atmel AT91SAM7X EK development board" + parent CYGPKG_HAL_ARM_AT91SAM7 + define_header hal_arm_at91sam7xek.h + include_dir cyg/hal + hardware + description " + The AT91SAM7XEK HAL package provides the support needed to run + eCos on an Atmel AT91SAM7X-EK development board." + + compile at91sam7xek_misc.c + + requires { CYGHWR_HAL_ARM_AT91 == "AT91SAM7S" } + requires { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x256" || + CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x128" } +} Index: hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c =================================================================== RCS file: hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c diff -N hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c 2 Jun 2006 18:19:08 -0000 @@ -0,0 +1,77 @@ +/*========================================================================== +// +// at91sam7xek_misc.c +// +// HAL misc board support code for Atmel AT91SAM7X EK board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2006 Andrew Lunn +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): andrew lunn +// Contributors: Andrew Lunn, John Eigelaar +// Date: 2006-06-20 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include +#include + +#include // IO macros + +// The development board has four LEDs +void +hal_at91_led (int val) +{ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB19, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB20, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB21, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB22, AT91_PIN_OUT); + + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PB19, AT91_PIN_PULLUP_DISABLE); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PB20, AT91_PIN_PULLUP_DISABLE); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PB21, AT91_PIN_PULLUP_DISABLE); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PB22, AT91_PIN_PULLUP_DISABLE); + + // Set the bits. The logic is inverted + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PB19, !(val & 1)); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PB20, !(val & 2)); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PB21, !(val & 4)); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PB22, !(val & 8)); +} + +//-------------------------------------------------------------------------- +// EOF at91sam7sek_misc.c