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Re: [ECOS] Re: ISR not causing an DSR in some rare conditions


Jay Foster <jay@systech.com> writes:
> I've re-examined this patch, and have noticed that it does not 'exactly'
> result in the same operation as the original code.
>
> The original code:
>         sub     ip,sp,#20
>         stmfd   ip!,{sp,lr}
>         mov     sp,ip
>         stmfd   sp!,{r0-r10,fp,ip}
>  
> The proposed code:
>         mov     ip,sp
>         sub     sp,sp,#(ARMREG_SIZE - armreg_pc) // skip svc_sp, svc_lr,
> vector, cpsr, and pc
>         stmfd   sp!,{ip,lr}
>         stmfd   sp!,{r0-r10,fp,ip}
>  
> Note that the value of 'ip' saved on the stack by the 4th instruction
> (stmfd) is different for these two cases.  In the original code, 'ip' was
> the same as the sp just prior to the stmfd instruction.  In the proposed
> code, 'ip' is the same as the sp upon entry to the function.
>
> By adding an extra instruction, this can be corrected to be the same:
>         mov     ip,sp
>         sub     sp,sp,#(ARMREG_SIZE - armreg_pc) // skip svc_sp, svc_lr,
> vector, cpsr, and pc
>         stmfd   sp!,{ip,lr}
>         mov     ip,sp
>         stmfd   sp!,{r0-r10,fp,ip}
>  
> It doesn't appear to make any difference.  Is this because it doesn't
> matter?

I believe it doesn't in fact matter as in both cases the ip stored on
the stack doesn't match those on the entry to the function. Thus, in
both cases the ip value is not preserved by the function. That's OK from
the point of view of ARM ABI as it says that caller must expect ip to be
clobbered by any function.

>From the point of view of eCos, both variants are equally not excellent
when saving of full CPU context is configured as the ip saved in the
thread context doesn't match the ip of the thread though it could only
affect the ease of debugging, I think.

> If it doesn't matter, then there is no reason to add the extra mov
> instruction.

There is no reason to add extra instruction, I think.

> Are interrupts even enabled on entry to this function?  If not, then
> none of this matters.

I believe that interrupts are enabled during context switch, so the
change I've proposed does matter.

-- Sergei.


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