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SH4 sh7751r register patch
- From: Hajime Ishitani <pigmon at mail dot snd dot co dot jp>
- To: ecos-patches at sources dot redhat dot com
- Date: Fri, 20 May 2005 18:45:40 +0900
- Subject: SH4 sh7751r register patch
Hello
I made two patches for SH4.
1. Added of 12 multiply mode of PLL1. (SH7751R)
2. Typo of rtc register address. (SH7751/SH7751R)
Index: ecos/packages/hal/sh/sh4/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/sh/sh4/current/ChangeLog,v
retrieving revision 1.22
diff -u -r1.22 ChangeLog
--- ecos/packages/hal/sh/sh4/current/ChangeLog 22 Apr 2004 15:26:52 -0000 1.22
+++ ecos/packages/hal/sh/sh4/current/ChangeLog 20 May 2005 05:51:30 -0000
@@ -1,3 +1,10 @@
+2005-05-13 Hajime Ishitani <pigmon@mail.snd.co.jp>
+
+ * include/mod_regs_cpg.h :
+ added CYGHWR_HAL_SH_OOC_PLL_1 12 multiply(SH7751R).
+
+ * include/mod_regs_rtc.h : Fix register address typos.
+
2004-04-22 Jani Monoses <jani@iv.ro>
* cdl/hal_sh_sh4.cdl :
Index: ecos/packages/hal/sh/sh4/current/include/mod_regs_cpg.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/sh/sh4/current/include/mod_regs_cpg.h,v
retrieving revision 1.4
diff -u -r1.4 mod_regs_cpg.h
--- ecos/packages/hal/sh/sh4/current/include/mod_regs_cpg.h 5 Dec 2003 17:07:30 -0000 1.4
+++ ecos/packages/hal/sh/sh4/current/include/mod_regs_cpg.h 20 May 2005 05:36:55 -0000
@@ -92,6 +92,8 @@
# define CYGARC_REG_FRQCR_INIT_PLL1 0x0400
#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 8)
# define CYGARC_REG_FRQCR_INIT_PLL1 0x0400
+#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 12)
+# define CYGARC_REG_FRQCR_INIT_PLL1 0x0400
#else
# error "Unsupported PLL1 setting"
#endif
Index: ecos/packages/hal/sh/sh4/current/include/mod_regs_rtc.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/sh/sh4/current/include/mod_regs_rtc.h,v
retrieving revision 1.3
diff -u -r1.3 mod_regs_rtc.h
--- ecos/packages/hal/sh/sh4/current/include/mod_regs_rtc.h 23 May 2002 23:05:04 -0000 1.3
+++ ecos/packages/hal/sh/sh4/current/include/mod_regs_rtc.h 20 May 2005 05:36:55 -0000
@@ -1,86 +1,88 @@
-//=============================================================================
-//
-// mod_regs_rtc.h
-//
-// RTC (real time clock) Module register definitions
-//
-//=============================================================================
-//####ECOSGPLCOPYRIGHTBEGIN####
-// -------------------------------------------
-// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-//
-// eCos is free software; you can redistribute it and/or modify it under
-// the terms of the GNU General Public License as published by the Free
-// Software Foundation; either version 2 or (at your option) any later version.
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-// for more details.
-//
-// You should have received a copy of the GNU General Public License along
-// with eCos; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-//
-// As a special exception, if other files instantiate templates or use macros
-// or inline functions from this file, or you compile this file and link it
-// with other works to produce a work based on this file, this file does not
-// by itself cause the resulting work to be covered by the GNU General Public
-// License. However the source code for this file must still be made available
-// in accordance with section (3) of the GNU General Public License.
-//
-// This exception does not invalidate any other reasons why a work based on
-// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
-// -------------------------------------------
-//####ECOSGPLCOPYRIGHTEND####
-//=============================================================================
-//#####DESCRIPTIONBEGIN####
-//
-// Author(s): jskov
-// Contributors:jskov
-// Date: 2000-10-30
-//
-//####DESCRIPTIONEND####
-//
-//=============================================================================
-
-//--------------------------------------------------------------------------
-// RealTime Clock
-
-#define CYGARC_REG_RC64CNT 0xfffffec0
-#define CYGARC_REG_RSECCNT 0xfffffec2
-#define CYGARC_REG_RMINCNT 0xfffffec4
-#define CYGARC_REG_RHRCNT 0xfffffec6
-#define CYGARC_REG_RWKCNT 0xfffffec8
-#define CYGARC_REG_RDAYCNT 0xfffffeca
-#define CYGARC_REG_RMONCNT 0xfffffecc
-#define CYGARC_REG_RYRCNT 0xfffffece
-#define CYGARC_REG_RSECAR 0xfffffed0
-#define CYGARC_REG_RMINAR 0xfffffed2
-#define CYGARC_REG_RHRAR 0xfffffed4
-#define CYGARC_REG_RWKAR 0xfffffed6
-#define CYGARC_REG_RDAYAR 0xfffffed8
-#define CYGARC_REG_RMONAR 0xfffffeda
-#define CYGARC_REG_RCR1 0xfffffedc
-#define CYGARC_REG_RCR2 0xfffffede
-
-
-#define CYGARC_REG_RCR1_CF 0x80 // carry flag
-#define CYGARC_REG_RCR1_CIE 0x10 // carry interrupt enable
-#define CYGARC_REG_RCR1_AIE 0x08 // alarm interrupt enable
-#define CYGARC_REG_RCR1_AF 0x01 // alarm flag
-
-#define CYGARC_REG_RCR2_PEF 0x80 // periodic interrupt flag
-#define CYGARC_REG_RCR2_PES2 0x40 // periodic interrupt setting
-#define CYGARC_REG_RCR2_PES1 0x20
-#define CYGARC_REG_RCR2_PES0 0x10
-#define CYGARC_REG_RCR2_RTCEN 0x08 // RTC enable
-#define CYGARC_REG_RCR2_ADJ 0x04 // second adjustment
-#define CYGARC_REG_RCR2_RESET 0x02 // reset
-#define CYGARC_REG_RCR2_START 0x01 // start
-
-
+//=============================================================================
+//
+// mod_regs_rtc.h
+//
+// RTC (real time clock) Module register definitions
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors:jskov
+// Date: 2000-10-30
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//--------------------------------------------------------------------------
+// RealTime Clock
+
+#define CYGARC_REG_RC64CNT 0xFFC80000 // 8bit
+#define CYGARC_REG_RSECCNT 0xFFC80004 // 8bit
+#define CYGARC_REG_RMINCNT 0xFFC80008 // 8bit
+#define CYGARC_REG_RHRCNT 0xFFC8000C // 8bit
+#define CYGARC_REG_RWKCNT 0xFFC80010 // 8bit
+#define CYGARC_REG_RDAYCNT 0xFFC80014 // 8bit
+#define CYGARC_REG_RMONCNT 0xFFC80018 // 8bit
+#define CYGARC_REG_RYRCNT 0xFFC8001C // 16bit
+#define CYGARC_REG_RSECAR 0xFFC80020 // 8bit
+#define CYGARC_REG_RMINAR 0xFFC80024 // 8bit
+#define CYGARC_REG_RHRAR 0xFFC80028 // 8bit
+#define CYGARC_REG_RWKAR 0xFFC8002C // 8bit
+#define CYGARC_REG_RDAYAR 0xFFC80030 // 8bit
+#define CYGARC_REG_RMONAR 0xFFC80034 // 8bit
+#define CYGARC_REG_RCR1 0xFFC80038 // 8bit
+#define CYGARC_REG_RCR2 0xFFC8003C // 8bit
+#define CYGARC_REG_RCR3 0xFFC80050 // 8bit
+#define CYGARC_REG_RYRAR 0xFFC80054 // 8bit
+
+
+#define CYGARC_REG_RCR1_CF 0x80 // carry flag
+#define CYGARC_REG_RCR1_CIE 0x10 // carry interrupt enable
+#define CYGARC_REG_RCR1_AIE 0x08 // alarm interrupt enable
+#define CYGARC_REG_RCR1_AF 0x01 // alarm flag
+
+#define CYGARC_REG_RCR2_PEF 0x80 // periodic interrupt flag
+#define CYGARC_REG_RCR2_PES2 0x40 // periodic interrupt setting
+#define CYGARC_REG_RCR2_PES1 0x20
+#define CYGARC_REG_RCR2_PES0 0x10
+#define CYGARC_REG_RCR2_RTCEN 0x08 // RTC enable
+#define CYGARC_REG_RCR2_ADJ 0x04 // second adjustment
+#define CYGARC_REG_RCR2_RESET 0x02 // reset
+#define CYGARC_REG_RCR2_START 0x01 // start
+
+
--
Hajime Ishitani
.