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Added RTL8201 PHY support to ks32c5000 ethernet driver
- From: Roland Caßebohm <roland dot cassebohm at visionsystems dot de>
- To: ecos-patches at sources dot redhat dot com
- Date: Thu, 9 Oct 2003 18:15:14 +0200
- Subject: Added RTL8201 PHY support to ks32c5000 ethernet driver
2003-10-09 Roland Cassebohm <roland.cassebohm@visionsystems.de>
* src/rtl8201.c: New file. Added RTL8201 PHY support.
* cdl/ks32c5000_eth.cdl: CDL to allow configuration of the above.
--
___________________________________________________
VS Vision Systems GmbH, Industrial Image Processing
Dipl.-Ing. Roland Caßebohm
Aspelohe 27A, D-22848 Norderstedt, Germany
http://www.visionsystems.de
___________________________________________________
Index: packages/devs/eth/arm/ks32c5000//current/ChangeLog
===================================================================
RCS file: /home/cassebohm/net/USERS/CVSROOT/VSprojects/ecos/packages/devs/eth/arm/ks32c5000/current/ChangeLog,v
retrieving revision 1.1.1.1
diff -u -5 -p -r1.1.1.1 ChangeLog
--- packages/devs/eth/arm/ks32c5000//current/ChangeLog 29 Sep 2003 15:15:43 -0000 1.1.1.1
+++ packages/devs/eth/arm/ks32c5000//current/ChangeLog 9 Oct 2003 13:53:47 -0000
@@ -1,5 +1,10 @@
+2003-10-09 Roland Cassebohm <roland.cassebohm@visionsystems.de>
+
+ * src/rtl8201.c: New file. Added RTL8201 PHY support.
+ * cdl/ks32c5000_eth.cdl: CDL to allow configuration of the above.
+
2003-06-24 Jonathan Larmour <jifl@eCosCentric.com>
* src/ks5000_ether.c: Some tidies of the previous changes.
* cdl/ks32c5000_eth.cdl: Clarify option description and rename
CYGVAR_DEVS_ETH_ARM_KS32C5000_REDBOOT_HOLDS_ESA_ETH0 to
Index: packages/devs/eth/arm/ks32c5000//current/cdl/ks32c5000_eth.cdl
===================================================================
RCS file: /home/cassebohm/net/USERS/CVSROOT/VSprojects/ecos/packages/devs/eth/arm/ks32c5000/current/cdl/ks32c5000_eth.cdl,v
retrieving revision 1.1.1.1
retrieving revision 1.1.1.1.2.1
diff -u -5 -p -r1.1.1.1 -r1.1.1.1.2.1
--- packages/devs/eth/arm/ks32c5000//current/cdl/ks32c5000_eth.cdl 29 Sep 2003 15:15:43 -0000 1.1.1.1
+++ packages/devs/eth/arm/ks32c5000//current/cdl/ks32c5000_eth.cdl 8 Oct 2003 16:37:04 -0000 1.1.1.1.2.1
@@ -145,10 +145,18 @@ cdl_package CYGPKG_DEVS_ETH_ARM_KS32C500
"TEST_BLINK_SLOW"}
default_value {"LINK_ACTIVITY"}
}
}
+ cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_RTL8201 {
+ display "RTL8201 PHY support"
+ flavor bool
+ default_value 0
+ implements CYGINT_DEVS_ETH_ARM_KS32C5000_PHY
+ compile -library=libextras.a rtl8201.c
+ }
+
cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR {
display "PHY MII address"
flavor data
legal_values 0 to 31
default_value 1
Index: packages/devs/eth/arm/ks32c5000//current/src/rtl8201.c
===================================================================
RCS file: packages/devs/eth/arm/ks32c5000//current/src/rtl8201.c
diff -N packages/devs/eth/arm/ks32c5000//current/src/rtl8201.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ packages/devs/eth/arm/ks32c5000//current/src/rtl8201.c 9 Oct 2003 13:50:05 -0000
@@ -0,0 +1,170 @@
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_if.h>
+
+#include <pkgconf/devs_eth_arm_ks32c5000.h>
+
+#include "std.h"
+#include "phy.h"
+
+// Set up the level of debug output
+#if CYGPKG_DEVS_ETH_ARM_KS32C5000_DEBUG_LEVEL > 0
+#define debug1_printf(args...) diag_printf(args)
+#else
+#define debug1_printf(args...) /* noop */
+#endif
+#if CYGPKG_DEVS_ETH_ARM_KS32C5000_DEBUG_LEVEL > 1
+#define debug2_printf(args...) diag_printf(args)
+#else
+#define debug2_printf(args...) /* noop */
+#endif
+
+// address of the RTL8201 phy
+#ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR
+#define RTL8201_ADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR
+#else
+#warning no Phy addr set
+#define RTL8201_ADDR 1
+#endif
+
+// RTL8201 register offsets
+#define RTL8201_CNTL_REG 0x00
+#define RTL8201_STATUS_REG 0x01
+#define RTL8201_ID_REG1 0x02
+#define RTL8201_ID_REG2 0x03
+#define RTL8201_ANA_REG 0x04
+#define RTL8201_ANLPA_REG 0x05
+#define RTL8201_ANE_REG 0x06
+#define RTL8201_NSR_REG 0x10
+#define RTL8201_LBREMR_REG 0x11
+#define RTL8201_RXER_REG 0x12
+#define RTL8201_10M_NIC_REG 0x13
+#define RTL8201_PHY1_1_REG 0x14
+#define RTL8201_PHY1_2_REG 0x15
+#define RTL8201_PHY2_REG 0x16
+#define RTL8201_TWISTER1_REG 0x17
+#define RTL8201_TWISTER2_REG 0x18
+#define RTL8201_TEST_REG 0x19
+
+// RTL8201 Control register bit defines
+#define RTL8201_CNTL_RESET 0x8000
+#define RTL8201_CNTL_LOOPBACK 0x4000
+#define RTL8201_CNTL_SPEED 0x2000 // 1=100Meg, 0=10Meg
+#define RTL8201_CNTL_AN 0x1000 // 1=Enable auto negotiation, 0=disable it
+#define RTL8201_CNTL_PWRDN 0x0800 // 1=Enable power down
+#define RTL8201_CNTL_RSTRT_AN 0x0200 // 1=Restart Auto Negotioation process
+#define RTL8201_CNTL_FULL_DUP 0x0100 // 1=Enable full duplex mode, 0=half dup
+
+#define Bit(n) (1<<(n))
+
+#define RTL8201_STATUS_100T4 Bit(15)
+#define RTL8201_STATUS_100TX_FULL Bit(14)
+#define RTL8201_STATUS_100TX Bit(13)
+#define RTL8201_STATUS_10T_FULL Bit(12)
+#define RTL8201_STATUS_10T Bit(11)
+#define RTL8201_STATUS_AN_COMLETE Bit(5)
+#define RTL8201_STATUS_LINKUP Bit(2)
+
+#define RTL8201_ANA_PAUSE_ENA Bit(10)
+#define RTL8201_ANA_100T4 Bit(9)
+#define RTL8201_ANA_100TX_FULL Bit(8)
+#define RTL8201_ANA_100TX Bit(7)
+#define RTL8201_ANA_10T_FULL Bit(6)
+#define RTL8201_ANA_10T Bit(5)
+#define RTL8201_ANA_SEL_802_3 Bit(0)
+
+#define RTL8201_TEST_LINK_10 Bit(1)
+#define RTL8201_TEST_LINK_100 Bit(0)
+#define RTL8201_TEST_PHY_ADR (0x1f<<8)
+
+static int do_autonegotation=0;
+
+#ifndef CYGPKG_KERNEL
+#define DEBUG_PRINTF(format, a...) diag_printf(format, ## a)
+#else
+#define DEBUG_PRINTF(format, a...)
+#endif
+
+void PhyReset(void)
+{
+ static int init_done=0;
+ unsigned Status;
+
+ if (init_done)
+ return;
+
+ init_done=1;
+
+ debug2_printf("Phy addr %d\n",RTL8201_ADDR);
+ // first software reset the RTL8201
+ MiiStationWrite(RTL8201_CNTL_REG, RTL8201_ADDR, RTL8201_CNTL_RESET);
+ MiiStationWrite(RTL8201_CNTL_REG, RTL8201_ADDR, 0);
+
+#if 1
+ // initialize auto-negotiation capabilities
+ MiiStationWrite(RTL8201_ANA_REG,RTL8201_ADDR,
+ RTL8201_ANA_100TX_FULL+
+ RTL8201_ANA_100TX+
+ RTL8201_ANA_10T_FULL+
+ RTL8201_ANA_10T+
+ RTL8201_ANA_SEL_802_3);
+ // Now start an auto negotiation
+ debug2_printf("Start auto negotiation\n");
+ MiiStationWrite(RTL8201_CNTL_REG, RTL8201_ADDR,
+ RTL8201_CNTL_AN+
+ RTL8201_CNTL_RSTRT_AN);
+#elif 0
+#warning force to 10M full duplex
+ // initialize auto-negotiation capabilities
+ MiiStationWrite(RTL8201_ANA_REG,RTL8201_ADDR,
+ RTL8201_ANA_10T_FULL+
+ RTL8201_ANA_10T+
+ RTL8201_ANA_SEL_802_3);
+ // force to 10M full duplex
+ MiiStationWrite(RTL8201_CNTL_REG, RTL8201_ADDR,
+ RTL8201_CNTL_FULL_DUP);
+#else
+#warning force to 10M half duplex
+ // initialize auto-negotiation capabilities
+ MiiStationWrite(RTL8201_ANA_REG,RTL8201_ADDR,
+ RTL8201_ANA_10T+
+ RTL8201_ANA_SEL_802_3);
+ // force to 10M half duplex
+ MiiStationWrite(RTL8201_CNTL_REG, RTL8201_ADDR,
+ 0);
+#endif
+}
+
+unsigned PhyStatus(void)
+{
+ unsigned Status;
+ unsigned r = 0, count=0;
+
+ // Wait for auto negotiation to get completed
+ do
+ {
+ Status = MiiStationRead(RTL8201_STATUS_REG,RTL8201_ADDR);
+ CYGACC_CALL_IF_DELAY_US(10000);
+ count++;
+ }
+ while (!(Status&RTL8201_STATUS_AN_COMLETE) && count<500);
+ //If it takes longer then 5 sec stop waiting
+
+ Status = MiiStationRead(RTL8201_STATUS_REG,RTL8201_ADDR);
+ if (Status & RTL8201_STATUS_LINKUP)
+ r |= PhyStatus_LinkUp;
+ Status = MiiStationRead(RTL8201_CNTL_REG,RTL8201_ADDR);
+ if (Status & RTL8201_CNTL_FULL_DUP)
+ r |= PhyStatus_FullDuplex;
+ Status = MiiStationRead(RTL8201_TEST_REG,RTL8201_ADDR);
+ if (Status & RTL8201_TEST_LINK_100)
+ r |= PhyStatus_100Mb;
+
+ debug2_printf("PhyStatus=0x%x\n",r);
+
+ return r;
+}
+
+void PhyInterruptAck(void)
+{
+}