Re: RealTek 8139 driver, 2. revision

[Eric Doenges <Eric dot Doenges at DynaPel dot de>]

Gary Thomas wrote:

>   * I experienced problems with the Rx buffer data because the buffers
>     were cacheable.  On some systems (this one and most PowerPC), the
>     CPU may not see changes to data which happens to already be in the
>     CPU cache.  I got around this by using a non-cached address to
>     access the Rx data.  n.b. this may not be sufficient for all 
>     platforms.

I was thinking about this yesterday evening and added a
CYGARC_UNCACHED_ADDRESS() to the transmit buffer as well. However, to be
completely portable (there might be architectures/platforms that do not 
support uncached memory ranges) I think a HAL_DCACHE_SYNC() should be
added in the following places:

a) after copying data to the transmit buffer
b) before reading the packet header from the receive buffer
c) before copying data from the receive buffer

I think this needs to be configurable, since flushing the data cache on
architectures that don't need it would generate an unnecessary
performance hit. Is there a preferred method for doing this, i.e any
#define that would tell me if flushing the cache is necessary or not ?
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