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KS32C5000 (S3C4510B) Ethernet Driver Patches
- From: Jay Foster <jay at systech dot com>
- To: "'ecos-patches at sources dot redhat dot com'" <ecos-patches at sources dot redhat dot com>
- Date: Tue, 25 Feb 2003 09:48:35 -0800
- Subject: KS32C5000 (S3C4510B) Ethernet Driver Patches
Attached is a patch for the Samsung KS32C5000 (S3C4510B) ethernet driver.
It adds a configurable PHY MII address and the ETH_DRV_SET_MAC_ADDRESS ioctl
to support setting the ethernet address from the application.
Index: current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/ChangeLog,v
retrieving revision 1.9
diff -u -5 -p -r1.9 ChangeLog
--- current/ChangeLog 20 Feb 2003 23:22:33 -0000 1.9
+++ current/ChangeLog 25 Feb 2003 17:00:54 -0000
@@ -1,5 +1,19 @@
+2003-02-25 Jay Foster <jay at systech dot com>
+
+ * src/ics1890.c: Added configurable PHY MII address.
+ * src/lxt970.c: Added configurable PHY MII address.
+ * src/lxt972.c: Added configurable PHY MII address.
+ * cdl/ks32c5000_eth.cdl: CDL to allow configuration of the PHY
+ MII address. Documented support for ICS1893AF PHY.
+ * src/ks5000_ether.c: Added configurable PHY MII address.
+ Fixed local definition of eth_drv_init() macro (produces no code
+ change). Fixed strncpy()s for the ETH_DRV_GET_IF_STATS IOCTL to
+ leave room for the NUL termination character and use parenthesis
+ with the 'sizeof' operator. Added ETH_DRV_SET_MAC_ADDRESS IOCTL
+ support to allow setting the MAC (ESA) address from the application.
+
2003-02-20 Chris Garry <cgarry at sweeneydesign dot co dot uk>
* src/ks5000_ether.c:
Removed line setting up programmable I/O pins as debug outputs.
cvs server: Diffing current/cdl
Index: current/cdl/ks32c5000_eth.cdl
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/cdl/ks32c5000_eth.cdl
,v
retrieving revision 1.5
diff -u -5 -p -r1.5 ks32c5000_eth.cdl
--- current/cdl/ks32c5000_eth.cdl 5 Nov 2002 02:50:13 -0000 1.5
+++ current/cdl/ks32c5000_eth.cdl 25 Feb 2003 17:00:54 -0000
@@ -81,13 +81,15 @@ cdl_package CYGPKG_DEVS_ETH_ARM_KS32C500
display "ICS1890 PHY support"
flavor bool
default_value 0
implements CYGINT_DEVS_ETH_ARM_KS32C5000_PHY
compile -library=libextras.a ics1890.c
+ description "This component provides support for the ICS1890
and
+ ICS1893AF PHY"
}
- cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT970 {
+ cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT970 {
display "LXT970 PHY support"
flavor bool
default_value 1
implements CYGINT_DEVS_ETH_ARM_KS32C5000_PHY
compile -library=libextras.a lxt970.c
@@ -99,39 +101,47 @@ cdl_package CYGPKG_DEVS_ETH_ARM_KS32C500
default_value 0
implements CYGINT_DEVS_ETH_ARM_KS32C5000_PHY
compile -library=libextras.a lxt972.c
no_define
- cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED1 {
+ cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED1 {
display "LED 1 mode"
flavor data
legal_values {"LINK_SPEED" "TX_ACTIVITY" "RX_ACTIVITY"
"COLLISION_STATUS" "LINK_STATUS" "DUPLEX_STATUS"
"LINK_ACTIVITY"
"LINK_STATUS_RX_STATUS_COMBINED" "LINK_STATUS_LINK_ACTIVITY_COMBINED"
"DUPLEX_STATUS_COLLISION_STATUS_COMBINED"
"TEST_ON" "TEST_OFF" "TEST_BLINK_FAST"
"TEST_BLINK_SLOW"}
default_value {"LINK_STATUS"}
}
- cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED2 {
+ cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED2 {
display "LED 2 mode"
flavor data
legal_values {"LINK_SPEED" "TX_ACTIVITY" "RX_ACTIVITY"
"COLLISION_STATUS" "LINK_STATUS" "DUPLEX_STATUS"
"LINK_ACTIVITY"
"LINK_STATUS_RX_STATUS_COMBINED" "LINK_STATUS_LINK_ACTIVITY_COMBINED"
"DUPLEX_STATUS_COLLISION_STATUS_COMBINED"
"TEST_ON" "TEST_OFF" "TEST_BLINK_FAST"
"TEST_BLINK_SLOW"}
default_value {"LINK_SPEED"}
}
- cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED3 {
+ cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED3 {
display "LED 3 mode"
flavor data
legal_values {"LINK_SPEED" "TX_ACTIVITY" "RX_ACTIVITY"
"COLLISION_STATUS" "LINK_STATUS" "DUPLEX_STATUS"
"LINK_ACTIVITY"
"LINK_STATUS_RX_STATUS_COMBINED" "LINK_STATUS_LINK_ACTIVITY_COMBINED"
"DUPLEX_STATUS_COLLISION_STATUS_COMBINED"
"TEST_ON" "TEST_OFF" "TEST_BLINK_FAST"
"TEST_BLINK_SLOW"}
default_value {"LINK_ACTIVITY"}
}
+ }
+
+ cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR {
+ display "PHY MII address"
+ flavor data
+ legal_values 0 to 31
+ default_value 1
+ description "This option specifies the MII address of the
PHY"
}
cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_MACADDR {
display "Ethernet address for eth0"
flavor data
cvs server: Diffing current/src
Index: current/src/ics1890.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/src/ics1890.c,v
retrieving revision 1.2
diff -u -5 -p -r1.2 ics1890.c
--- current/src/ics1890.c 23 May 2002 23:00:40 -0000 1.2
+++ current/src/ics1890.c 25 Feb 2003 17:00:54 -0000
@@ -65,11 +65,15 @@
#define PHY_ECNTL_REG1 0x10
#define PHY_QPDS_REG 0x11
#define PHY_10BOP_REG 0x12
#define PHY_ECNTL_REG2 0x13
-#define PHYHWADDR 0x20
+#ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR
+#define PHYHWADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR
+#else
+#define PHYHWADDR 1
+#endif
#define Bit(n) (1<<(n))
#define RESET_PHY Bit(15)
#define ENABLE_LOOPBACK Bit(14)
Index: current/src/ks5000_ether.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/src/ks5000_ether.c,v
retrieving revision 1.8
diff -u -5 -p -r1.8 ks5000_ether.c
--- current/src/ks5000_ether.c 20 Feb 2003 23:22:33 -0000 1.8
+++ current/src/ks5000_ether.c 25 Feb 2003 17:00:54 -0000
@@ -58,11 +58,11 @@
#if defined(CYGPKG_IO)
#include <pkgconf/io.h>
#include <cyg/io/io.h>
#include <cyg/io/devtab.h>
#else
-// need to prvide fake values for errno
+// need to provide fake values for errno
#define EIO 1
#define EINVAL 2
#endif
#include <cyg/infra/cyg_type.h> // Common type definitions and support
@@ -125,20 +125,20 @@
#define MiiStart 0x0800
void MiiStationWrite(U32 RegAddr, U32 PhyAddr, U32 PhyWrData)
{
STADATA = PhyWrData ;
- STACON = RegAddr | PhyAddr | MiiStart | PHYREGWRITE ;
+ STACON = RegAddr | (PhyAddr<<5) | MiiStart | PHYREGWRITE ;
while (STACON & MiiStart)
;
//debug_printf("PHY Wr %x:%02x := %04x\n",PhyAddr, RegAddr, PhyWrData) ;
}
U32 MiiStationRead(U32 RegAddr, U32 PhyAddr)
{
U32 PhyRdData;
- STACON = RegAddr | PhyAddr | MiiStart;
+ STACON = RegAddr | (PhyAddr<<5) | MiiStart;
while (STACON & MiiStart)
;
PhyRdData = STADATA;
//debug_printf("PHY Rd %x:%02x %04x\n",PhyAddr,RegAddr,PhyRdData) ;
return PhyRdData ;
@@ -1113,11 +1113,11 @@ typedef struct
}ks32c5000_priv_data_t;
ks32c5000_priv_data_t ks32c5000_priv_data;
#define eth_drv_tx_done(sc,key,retval)
(sc)->funs->eth_drv->tx_done(sc,key,retval)
-#define eth_drv_init(sc,enaddr) ((sc)->funs->eth_drv->init)(sc, myMacAddr)
+#define eth_drv_init(sc,enaddr) ((sc)->funs->eth_drv->init)(sc, enaddr)
#define eth_drv_recv(sc,len) ((sc)->funs->eth_drv->recv)(sc, len)
static unsigned char myMacAddr[6] = { CYGPKG_DEVS_ETH_ARM_KS32C5000_MACADDR
};
static bool ks32c5000_eth_init(struct cyg_netdevtab_entry *tab)
@@ -1177,15 +1177,38 @@ static int ks32c5000_eth_control(struct
case ETH_DRV_GET_IF_STATS_UD:
case ETH_DRV_GET_IF_STATS:
{
struct ether_drv_stats *p = (struct ether_drv_stats*)data;
*p = ifStats;
- strncpy(p->description,"description goes here",sizeof
p->description);
- strncpy(p->snmp_chipset,"chipset name",sizeof p->snmp_chipset);
+ strncpy(p->description,"description goes
here",sizeof(p->description)-1);
+ p->description[sizeof(p->description)-1] = '\0';
+ strncpy(p->snmp_chipset,"chipset
name",sizeof(p->snmp_chipset)-1);
+ p->snmp_chipset[sizeof(p->snmp_chipset)-1] = '\0';
return 0;
}
#endif
+ case ETH_DRV_SET_MAC_ADDRESS: {
+ int act;
+
+ if (ETHER_ADDR_LEN != len)
+ return -1;
+ debug_printf("ks32c5000_eth_control: ETH_DRV_SET_MAC_ADDRESS.\n");
+ act = ethernetRunning;
+ ks32c5000_eth_stop(sc);
+ ks32c5000_eth_start(sc, data, 0);
+ ethernetRunning = act;
+ return 0;
+ }
+#ifdef ETH_DRV_GET_MAC_ADDRESS
+ case ETH_DRV_GET_MAC_ADDRESS: {
+ if (len < ETHER_ADDR_LEN)
+ return -1;
+ debug_printf("ks32c5000_eth_control: ETH_DRV_GET_MAC_ADDRESS.\n");
+ memcpy(data, (void *)CAM_BaseAddr, ETHER_ADDR_LEN);
+ return 0;
+ }
+#endif
default:
return -1;
}
}
Index: current/src/lxt970.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/src/lxt970.c,v
retrieving revision 1.3
diff -u -5 -p -r1.3 lxt970.c
--- current/src/lxt970.c 5 Nov 2002 02:49:51 -0000 1.3
+++ current/src/lxt970.c 25 Feb 2003 17:00:54 -0000
@@ -53,11 +53,15 @@
#include "std.h"
#include "phy.h"
// address of the LX970 phy
-#define LX970_ADDR 0x20
+#ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR
+#define LX970_ADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR
+#else
+#define LX970_ADDR 1
+#endif
// LX970 register offsets
#define LX970_CNTL_REG 0x00
#define LX970_STATUS_REG 0x01
#define LX970_ID_REG1 0x02
Index: current/src/lxt972.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/eth/arm/ks32c5000/current/src/lxt972.c,v
retrieving revision 1.1
diff -u -5 -p -r1.1 lxt972.c
--- current/src/lxt972.c 5 Nov 2002 02:50:43 -0000 1.1
+++ current/src/lxt972.c 25 Feb 2003 17:00:54 -0000
@@ -57,11 +57,15 @@
#include "phy.h"
#define Bit(n) (1<<(n))
// address of the LX972 phy
-#define LX972_ADDR 0x00
+#ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR
+#define LX972_ADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR
+#else
+#define LX972_ADDR 0
+#endif
// LX972 register offsets
#define LX972_CTRL_REG 0x00
#define LX972_STATUS1_REG 0x01
#define LX972_PHY_ID1_REG 0x02
Jay Foster
jay at systech dot com