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AM33 virtual vector comm reorg
- From: Mark Salter <msalter at redhat dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: Tue, 19 Nov 2002 08:59:29 -0500 (EST)
- Subject: AM33 virtual vector comm reorg
This reorganizes the virtual vector comm support for AM33 targets.
It consolidates support for AM33 serial ports in one place. It also
allows platforms to choose which (if any) AM33 ports to use and to
define platform specific ports.
--Mark
Index: hal/mn10300/am33/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mn10300/am33/current/ChangeLog,v
retrieving revision 1.8
diff -u -p -5 -r1.8 ChangeLog
--- hal/mn10300/am33/current/ChangeLog 15 Nov 2002 18:05:21 -0000 1.8
+++ hal/mn10300/am33/current/ChangeLog 19 Nov 2002 13:52:17 -0000
@@ -1,5 +1,11 @@
+2002-11-19 Mark Salter <msalter@redhat.com>
+
+ * cdl/hal_mn10300_am33.cdl: Add virtual vector comm support using
+ any combination of AM33 serial ports and platform serial ports.
+ * src/am33_serial.c: New file. Support for internal serial ports.
+
2002-11-15 Mark Salter <msalter@redhat.com>
* cdl/hal_mn10300_am33.cdl: Add options to control placement of
VSR and virtual vector tables. Platforms may override.
* src/mn10300_am33.ld: Use new cdl option values.
Index: hal/mn10300/am33/current/cdl/hal_mn10300_am33.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mn10300/am33/current/cdl/hal_mn10300_am33.cdl,v
retrieving revision 1.7
diff -u -p -5 -r1.7 hal_mn10300_am33.cdl
--- hal/mn10300/am33/current/cdl/hal_mn10300_am33.cdl 15 Nov 2002 18:05:21 -0000 1.7
+++ hal/mn10300/am33/current/cdl/hal_mn10300_am33.cdl 19 Nov 2002 13:52:18 -0000
@@ -50,11 +50,13 @@
# ====================================================================
cdl_package CYGPKG_HAL_MN10300_AM33 {
display "MN10300 AM33 variant"
parent CYGPKG_HAL_MN10300
- implements CYGINT_HAL_MN10300_VARIANT
+ implements CYGINT_HAL_MN10300_VARIANT
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
hardware
include_dir cyg/hal
define_header hal_mn10300_am33.h
description "
The MN10300 AM33 variant HAL package provides generic
@@ -77,11 +79,11 @@ cdl_package CYGPKG_HAL_MN10300_AM33 {
define_proc {
puts $::cdl_header "#include <pkgconf/hal_mn10300.h>"
}
- compile var_misc.c variant.S
+ compile var_misc.c variant.S am33_serial.c
cdl_option CYGHWR_HAL_MN10300_PROCESSOR_OSC {
display "Processor Oscillator input"
flavor data
legal_values 16666667 to 33333333
@@ -159,10 +161,74 @@ cdl_package CYGPKG_HAL_MN10300_AM33 {
calculated { CYGHWR_HAL_MN10300_PLATFORM_VV_TABLE_BASE ?
CYGHWR_HAL_MN10300_PLATFORM_VV_TABLE_BASE : \
CYGHWR_HAL_MN10300_PLATFORM_VSR_TABLE_BASE + 0x100 }
description "
Base address of the virtual vectors table."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_AM33_SERIAL_CHANNELS {
+ display "Number of AM33 serial ports used on the board"
+ flavor data
+ calculated { (CYGSEM_HAL_AM33_PLF_USES_SERIAL0 && CYGSEM_HAL_AM33_PLF_USES_SERIAL1) ? 2 : \
+ (CYGSEM_HAL_AM33_PLF_USES_SERIAL0 || CYGSEM_HAL_AM33_PLF_USES_SERIAL1) ? 1 : \
+ 0 }
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated { CYGNUM_HAL_AM33_SERIAL_CHANNELS + \
+ CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS }
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Diagnostic serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The AM33 board has two serial ports. This option
+ chooses which port will be used for diagnostic output."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the diagnostic port.
+ Note: this should match the value chosen for the GDB port if the
+ diagnostic and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "Debug serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port."
}
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/mn10300_am33.ld
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
Index: hal/mn10300/am33/current/src/am33_serial.c
===================================================================
RCS file: hal/mn10300/am33/current/src/am33_serial.c
diff -N hal/mn10300/am33/current/src/am33_serial.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/mn10300/am33/current/src/am33_serial.c 19 Nov 2002 13:52:18 -0000
@@ -0,0 +1,568 @@
+//=============================================================================
+//
+// am33_serial.c
+//
+// Simple driver for the serial controllers on AM33 (MN103E) CPUs
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): dmoseley, dhowells
+// Contributors:msalter
+// Date: 2002-11-15
+// Description: Simple driver for the AM33 UARTs
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_TARGET_H
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // interface API
+#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
+
+#if !defined(CYGSEM_HAL_AM33_PLF_USES_SERIAL0) && !defined(CYGSEM_HAL_AM33_PLF_USES_SERIAL1)
+#define AM33_NUM_UARTS 0
+#elif defined(CYGSEM_HAL_AM33_PLF_USES_SERIAL0) && defined(CYGSEM_HAL_AM33_PLF_USES_SERIAL1)
+#define AM33_NUM_UARTS 2
+#else
+#define AM33_NUM_UARTS 1
+#endif
+
+#if AM33_NUM_UARTS > 0
+
+//-----------------------------------------------------------------------------
+// Base Registers
+#define AM33_SER0_BASE 0xD4002000
+#define AM33_SER1_BASE 0xD4002010
+
+/*---------------------------------------------------------------------------*/
+// AM33 Serial line
+
+#define _SERIAL_CR 0x00
+#define _SERIAL_ICR 0x04
+#define _SERIAL_TXR 0x08
+#define _SERIAL_RXR 0x09
+#define _SERIAL_SR 0x0c
+
+#define SERIAL0_CR ((volatile cyg_uint16 *)(AM33_SER0_BASE + _SERIAL_CR))
+#define SERIAL0_ICR ((volatile cyg_uint8 *) (AM33_SER0_BASE + _SERIAL_ICR))
+#define SERIAL0_TXR ((volatile cyg_uint8 *) (AM33_SER0_BASE + _SERIAL_TXR))
+#define SERIAL0_RXR ((volatile cyg_uint8 *) (AM33_SER0_BASE + _SERIAL_RXR))
+#define SERIAL0_SR ((volatile cyg_uint16 *)(AM33_SER0_BASE + _SERIAL_SR))
+
+#define SERIAL1_CR ((volatile cyg_uint16 *)(AM33_SER1_BASE + _SERIAL_CR))
+#define SERIAL1_ICR ((volatile cyg_uint8 *) (AM33_SER1_BASE + _SERIAL_ICR))
+#define SERIAL1_TXR ((volatile cyg_uint8 *) (AM33_SER1_BASE + _SERIAL_TXR))
+#define SERIAL1_RXR ((volatile cyg_uint8 *) (AM33_SER1_BASE + _SERIAL_RXR))
+#define SERIAL1_SR ((volatile cyg_uint16 *)(AM33_SER1_BASE + _SERIAL_SR))
+
+// Timer 0 provides a prescaler for lower baud rates
+#define TIMER0_MD ((volatile cyg_uint8 *)0xd4003000)
+#define TIMER0_BR ((volatile cyg_uint8 *)0xd4003010)
+
+// Timer 2 provides baud rate divisor
+#define TIMER2_MD ((volatile cyg_uint8 *)0xd4003002)
+#define TIMER2_BR ((volatile cyg_uint8 *)0xd4003012)
+
+// Timer 1 provides a prescaler for lower baud rates
+#define TIMER1_MD ((volatile cyg_uint8 *)0xd4003001)
+#define TIMER1_BR ((volatile cyg_uint8 *)0xd4003011)
+
+// Timer 3 provides baud rate divisor
+#define TIMER3_MD ((volatile cyg_uint8 *)0xd4003003)
+#define TIMER3_BR ((volatile cyg_uint8 *)0xd4003013)
+
+#define SIO_LSTAT_TRDY 0x20
+#define SIO_LSTAT_RRDY 0x10
+
+#define SIO_INT_ENABLE 0x11
+
+#define TMR_ENABLE 0x80
+#define TMR_SRC_IOCLOCK 0x00
+#define TMR_SRC_TMR0_UNDERFLOW 0x04
+
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+ cyg_uint8* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+ cyg_int32 baud_rate;
+} channel_data_t;
+
+static channel_data_t channels[AM33_NUM_UARTS] = {
+#if defined(CYGSEM_HAL_AM33_PLF_USES_SERIAL0) && !defined(HAL_PLATFORM_SERIAL1_FIRST)
+ { (cyg_uint8*)AM33_SER0_BASE, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_0_RX },
+#endif
+#ifdef CYGSEM_HAL_AM33_PLF_USES_SERIAL1
+ { (cyg_uint8*)AM33_SER1_BASE, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_1_RX },
+#endif
+#if defined(CYGSEM_HAL_AM33_PLF_USES_SERIAL0) && defined(HAL_PLATFORM_SERIAL1_FIRST)
+ { (cyg_uint8*)AM33_SER0_BASE, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_0_RX },
+#endif
+};
+
+//-----------------------------------------------------------------------------
+// Set the baud rate
+
+static cyg_uint32
+baud_divisor(int baud, int prescaler)
+{
+ cyg_uint32 divisor;
+
+ // divisor == INT(IOCLK/baud/8 + 0.5)
+ divisor = CYGHWR_HAL_MN10300_IOCLK_SPEED * 10;
+ divisor /= (baud / 100);
+ divisor /= prescaler;
+ divisor /= 8;
+ divisor += 500;
+ divisor /= 1000;
+ return divisor;
+}
+
+static int
+cyg_hal_plf_serial_set_baud(cyg_uint8* port, cyg_uint32 baud_rate)
+{
+ volatile cyg_uint8 *timer_base_reg;
+ volatile cyg_uint8 *timer_mode_reg;
+ cyg_uint32 divisor, prescaler;
+
+ if (port == (cyg_uint8*)AM33_SER0_BASE)
+ {
+ // SER0 uses TMR2
+ timer_base_reg = TIMER2_BR;
+ timer_mode_reg = TIMER2_MD;
+ } else if (port == (cyg_uint8*)AM33_SER1_BASE) {
+ // SER1 uses TMR3
+ timer_base_reg = TIMER3_BR;
+ timer_mode_reg = TIMER3_MD;
+ } else {
+ // Unknown port.
+ return -1;
+ }
+
+ switch (baud_rate)
+ {
+ case 1200:
+ case 2400:
+ case 4800:
+ case 9600:
+ case 19200:
+ case 38400:
+ case 57600:
+ case 115200:
+ case 230400:
+ break;
+
+ default:
+ // Unknown baud. Don't change anything
+ return -1;
+ }
+
+ for (prescaler = 1; prescaler <= 256; prescaler++) {
+ divisor = baud_divisor(baud_rate, prescaler);
+ if (divisor <= 256)
+ break;
+ }
+ --divisor;
+ --prescaler;
+
+ if (prescaler) {
+ HAL_WRITE_UINT8(TIMER0_BR, prescaler);
+ HAL_WRITE_UINT8(TIMER0_MD, TMR_ENABLE | TMR_SRC_IOCLOCK);
+ } else {
+ HAL_WRITE_UINT8(TIMER0_BR, 0);
+ HAL_WRITE_UINT8(TIMER0_MD, 0);
+ }
+
+ HAL_WRITE_UINT8(timer_base_reg, divisor);
+ HAL_WRITE_UINT8(timer_mode_reg, TMR_ENABLE |
+ (prescaler ? TMR_SRC_TMR0_UNDERFLOW : TMR_SRC_IOCLOCK));
+
+ return 0;
+}
+
+//-----------------------------------------------------------------------------
+// The minimal init, get and put functions. All by polling.
+
+static void
+cyg_hal_plf_serial_init_channel(void* __ch_data)
+{
+ cyg_uint8* port;
+
+ // Some of the diagnostic print code calls through here with no idea what the ch_data is.
+ // Go ahead and assume it is channels[0].
+ if (__ch_data == 0)
+ __ch_data = (void*)&channels[0];
+
+ port = ((channel_data_t*)__ch_data)->base;
+
+ // No interrupts for now.
+ HAL_WRITE_UINT8(port + _SERIAL_ICR, 0x00);
+
+ // Source from timer 2 or 3, 8bit chars, enable tx and rx
+ HAL_WRITE_UINT16(port + _SERIAL_CR, 0xc085);
+}
+
+static void
+cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch)
+{
+ cyg_uint8* port;
+ cyg_uint16 _status;
+
+ // Some of the diagnostic print code calls through here with no idea what the ch_data is.
+ // Go ahead and assume it is channels[0].
+ if (__ch_data == 0)
+ __ch_data = (void*)&channels[0];
+
+ port = ((channel_data_t*)__ch_data)->base;
+
+ do {
+ HAL_READ_UINT16(port + _SERIAL_SR, _status);
+ } while ((_status & SIO_LSTAT_TRDY) != 0);
+
+ HAL_WRITE_UINT8(port + _SERIAL_TXR, __ch);
+}
+
+static cyg_bool
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ cyg_uint8* port;
+ cyg_uint8 _status;
+
+ // Some of the diagnostic print code calls through here with no idea what the ch_data is.
+ // Go ahead and assume it is channels[0].
+ if (__ch_data == 0)
+ __ch_data = (void*)&channels[0];
+
+ port = ((channel_data_t*)__ch_data)->base;
+
+ HAL_READ_UINT8(port + _SERIAL_SR, _status);
+ if ((_status & SIO_LSTAT_RRDY) == 0)
+ return false;
+
+ HAL_READ_UINT8(port + _SERIAL_RXR, *ch);
+
+ // We must ack the interrupt caused by that read to avoid
+ // confusing the GDB stub ROM.
+ HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_0_RX );
+
+ return true;
+}
+
+static cyg_uint8
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+ CYGARC_HAL_SAVE_GP();
+
+ // Some of the diagnostic print code calls through here with no idea what the ch_data is.
+ // Go ahead and assume it is channels[0].
+ if (__ch_data == 0)
+ __ch_data = (void*)&channels[0];
+
+ while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ // Some of the diagnostic print code calls through here with no idea what the ch_data is.
+ // Go ahead and assume it is channels[0].
+ if (__ch_data == 0)
+ __ch_data = (void*)&channels[0];
+
+ while(__len-- > 0)
+ cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ // Some of the diagnostic print code calls through here with no idea what the ch_data is.
+ // Go ahead and assume it is channels[0].
+ if (__ch_data == 0)
+ __ch_data = (void*)&channels[0];
+
+ while(__len-- > 0)
+ *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan;
+ cyg_bool res;
+ CYGARC_HAL_SAVE_GP();
+
+ // Some of the diagnostic print code calls through here with no idea what the ch_data is.
+ // Go ahead and assume it is channels[0].
+ if (__ch_data == 0)
+ __ch_data = (void*)&channels[0];
+
+ chan = (channel_data_t*)__ch_data;
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+ for(;;) {
+ res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan;
+ cyg_uint8 icr;
+ int ret = 0;
+ CYGARC_HAL_SAVE_GP();
+
+ // Some of the diagnostic print code calls through here with no idea what the ch_data is.
+ // Go ahead and assume it is channels[0].
+ if (__ch_data == 0)
+ __ch_data = (void*)&channels[0];
+
+ chan = (channel_data_t*)__ch_data;
+
+ switch (__func) {
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+
+ HAL_READ_UINT8(chan->base + _SERIAL_ICR, icr);
+ icr |= SIO_INT_ENABLE;
+ HAL_WRITE_UINT8(chan->base + _SERIAL_ICR, icr);
+
+ HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ break;
+
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+
+ HAL_READ_UINT8(chan->base + _SERIAL_ICR, icr);
+ icr &= ~SIO_INT_ENABLE;
+ HAL_WRITE_UINT8(chan->base + _SERIAL_ICR, icr);
+
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ break;
+
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+
+ case __COMMCTL_SET_TIMEOUT:
+ {
+ va_list ap;
+
+ va_start(ap, __func);
+
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+ va_end(ap);
+ }
+ break;
+
+ case __COMMCTL_SETBAUD:
+ {
+ cyg_uint32 baud_rate;
+ cyg_uint8* port = chan->base;
+ va_list ap;
+
+ va_start(ap, __func);
+ baud_rate = va_arg(ap, cyg_uint32);
+ va_end(ap);
+
+ // Disable port interrupts while changing hardware
+ HAL_READ_UINT8(port + _SERIAL_ICR, icr);
+ HAL_WRITE_UINT8(port + _SERIAL_ICR, 0);
+
+ // Set baud rate.
+ ret = cyg_hal_plf_serial_set_baud(port, baud_rate);
+
+ // Reenable interrupts if necessary
+ HAL_WRITE_UINT8(port + _SERIAL_ICR, icr);
+ }
+ break;
+
+ case __COMMCTL_GETBAUD:
+ break;
+
+ default:
+ break;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ int res = 0;
+ channel_data_t* chan;
+ CYGARC_HAL_SAVE_GP();
+
+ // Some of the diagnostic print code calls through here with no idea what the ch_data is.
+ // Go ahead and assume it is channels[0].
+ if (__ch_data == 0)
+ __ch_data = (void*)&channels[0];
+
+ chan = (channel_data_t*)__ch_data;
+
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+#if 0
+ HAL_READ_UINT8(chan->base + SER_16550_IIR, _iir);
+ _iir &= SIO_IIR_ID_MASK;
+
+ *__ctrlc = 0;
+ if ((_iir == ISR_Rx_Avail) || (_iir == ISR_Rx_Char_Timeout)) {
+
+ HAL_READ_UINT8(chan->base + SER_16550_RBR, c);
+
+ if( cyg_hal_is_break( &c , 1 ) )
+ *__ctrlc = 1;
+
+ res = CYG_ISR_HANDLED;
+ }
+#endif
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+
+void
+cyg_hal_am33_serial_init(int first_chan)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+
+ for (i = 0; i < AM33_NUM_UARTS; i++) {
+
+ // Disable interrupts.
+ HAL_INTERRUPT_MASK(channels[0].isr_vector);
+
+ // Init channel
+ cyg_hal_plf_serial_init_channel((void*)&channels[i]);
+ cyg_hal_plf_serial_set_baud(channels[i].base, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
+
+ // Setup procs in the vector table
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i + first_chan);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void
+cyg_hal_plf_serial_setbaud(void *__ch_data, cyg_uint32 baud_rate)
+{
+ cyg_uint8* port;
+
+ // Some of the diagnostic print code calls through here with no idea what the ch_data is.
+ // Go ahead and assume it is channels[0].
+ if (__ch_data == 0)
+ __ch_data = (void*)&channels[0];
+
+ port = ((channel_data_t*)__ch_data)->base;
+
+ cyg_hal_plf_serial_set_baud(port, baud_rate);
+}
+
+
+// If the platform provides some channels of its own, then this function will be
+// provided by that platform.
+#if !defined(CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS) || !CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS
+void
+cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ cyg_hal_am33_serial_init(0);
+}
+#endif
+
+#endif // AM33_NUM_UARTS > 0
+
+/*---------------------------------------------------------------------------*/
+/* End of am33_serial.c */
Index: hal/mn10300/asb/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mn10300/asb/current/ChangeLog,v
retrieving revision 1.5
diff -u -p -5 -r1.5 ChangeLog
--- hal/mn10300/asb/current/ChangeLog 15 Nov 2002 18:05:22 -0000 1.5
+++ hal/mn10300/asb/current/ChangeLog 19 Nov 2002 13:52:18 -0000
@@ -1,5 +1,11 @@
+2002-11-19 Mark Salter <msalter@redhat.com>
+
+ * cdl/hal_mn10300_am33_asb.cdl: Remove virtual vector comm support.
+ Add options to select AM33 serial ports for comm channels.
+ * src/ser_asb.c: Remove.
+
2002-11-15 Mark Salter <msalter@redhat.com>
* cdl/hal_mn10300_am33_asb.cdl: Override default VSR placement.
* include/pkgconf/mlt_mn10300_am33_asb_ram.ldi: Remove unneeded defines.
* include/pkgconf/mlt_mn10300_am33_asb_flash.ldi: Ditto.
Index: hal/mn10300/asb/current/cdl/hal_mn10300_am33_asb.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mn10300/asb/current/cdl/hal_mn10300_am33_asb.cdl,v
retrieving revision 1.4
diff -u -p -5 -r1.4 hal_mn10300_am33_asb.cdl
--- hal/mn10300/asb/current/cdl/hal_mn10300_am33_asb.cdl 15 Nov 2002 18:05:22 -0000 1.4
+++ hal/mn10300/asb/current/cdl/hal_mn10300_am33_asb.cdl 19 Nov 2002 13:52:19 -0000
@@ -59,25 +59,24 @@ cdl_package CYGPKG_HAL_MN10300_AM33_ASB
description "
The ASB HAL package should be used when targetting the
actual hardware for the Panasonic ASB2303 Evaluation Board
with the MN103E010 microcontroller."
- compile hal_diag.c plf_stub.c plf_misc.c ser_asb.c
+ compile hal_diag.c plf_stub.c plf_misc.c
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
- implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
- implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
requires CYGSEM_HAL_UNCACHED_FLASH_ACCESS == 1;
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_mn10300_am33.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_mn10300_am33_asb.h>"
puts $::cdl_system_header "#define HAL_PLATFORM_BOARD \"Panasonic ASB2303\""
puts $::cdl_system_header "#define HAL_PLATFORM_EXTRA \"\""
puts $::cdl_system_header "#define HAL_PLATFORM_CPU \"MN103E010 AM33/2.0\""
+ puts $::cdl_system_header "#define HAL_PLATFORM_SERIAL1_FIRST"
}
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
@@ -113,65 +112,10 @@ cdl_package CYGPKG_HAL_MN10300_AM33_ASB
default_value 0x8C000000
description "
Base address of the VSR table on ASB2303 board."
}
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
- display "Default console channel."
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- calculated 0
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
- display "Number of communication channels on the board"
- flavor data
- calculated 2
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
- display "Debug serial port"
- active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- This option chooses which port will be used to connect to a host
- running GDB."
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
- display "Diagnostic serial port"
- active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
- description "
- The ASB2303 board has two serial ports. This option
- chooses which port will be used for diagnostic output."
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
- display "Diagnostic serial port baud rate"
- flavor data
- legal_values 9600 19200 38400 57600 115200
- default_value 115200
- description "
- This option selects the baud rate used for the diagnostic port.
- Note: this should match the value chosen for the GDB port if the
- diagnostic and GDB port are the same."
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
- display "GDB serial port baud rate"
- flavor data
- legal_values 9600 19200 38400 57600 115200
- default_value 115200
- description "
- This option selects the baud rate used for the GDB port."
- }
-
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
description "
@@ -241,10 +185,28 @@ cdl_package CYGPKG_HAL_MN10300_AM33_ASB
display "Number of breakpoints supported by the HAL."
flavor data
default_value 25
description "
This option determines the number of breakpoints supported by the HAL."
+ }
+
+ cdl_option CYGSEM_HAL_AM33_PLF_USES_SERIAL0 {
+ display "ASB2303 uses AM33 SERIAL0"
+ flavor bool
+ default_value 1
+ description "
+ Enable this option if AM33 SERIAL0 is to be used as a virtual vector
+ communications channel."
+ }
+
+ cdl_option CYGSEM_HAL_AM33_PLF_USES_SERIAL1 {
+ display "ASB2303 uses AM33 SERIAL1"
+ flavor bool
+ default_value 1
+ description "
+ Enable this option if AM33 SERIAL1 is to be used as a virtual vector
+ communications channel."
}
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
Index: hal/mn10300/asb2305/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mn10300/asb2305/current/ChangeLog,v
retrieving revision 1.5
diff -u -p -5 -r1.5 ChangeLog
--- hal/mn10300/asb2305/current/ChangeLog 15 Nov 2002 18:05:23 -0000 1.5
+++ hal/mn10300/asb2305/current/ChangeLog 19 Nov 2002 13:52:19 -0000
@@ -1,5 +1,11 @@
+2002-11-19 Mark Salter <msalter@redhat.com>
+
+ * cdl/hal_mn10300_am33_asb2305.cdl: Remove virtual vector comm support.
+ Add option to select platform serial port for comm channels. Add rules
+ to build RedBoot srec amd img file.
+
2002-11-15 Mark Salter <msalter@redhat.com>
* cdl/hal_mn10300_am33_asb2305.cdl: Override default VSR placement.
Removed unused options. Set correct clock speed.
* include/pkgconf/mlt_mn10300_am33_asb2305_ram.ldi: Remove unneeded
Index: hal/mn10300/asb2305/current/cdl/hal_mn10300_am33_asb2305.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mn10300/asb2305/current/cdl/hal_mn10300_am33_asb2305.cdl,v
retrieving revision 1.5
diff -u -p -5 -r1.5 hal_mn10300_am33_asb2305.cdl
--- hal/mn10300/asb2305/current/cdl/hal_mn10300_am33_asb2305.cdl 15 Nov 2002 18:05:23 -0000 1.5
+++ hal/mn10300/asb2305/current/cdl/hal_mn10300_am33_asb2305.cdl 19 Nov 2002 13:52:19 -0000
@@ -63,11 +63,10 @@ cdl_package CYGPKG_HAL_MN10300_AM33_ASB2
compile hal_diag.c plf_stub.c plf_misc.c ser_asb.c
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
- implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
requires CYGSEM_HAL_UNCACHED_FLASH_ACCESS == 1;
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_mn10300_am33.h>"
@@ -188,55 +187,23 @@ cdl_package CYGPKG_HAL_MN10300_AM33_ASB2
default_value 25
description "
This option determines the number of breakpoints supported by the HAL."
}
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
- display "Number of communication channels on the board"
- flavor data
- calculated 1
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
- display "Debug serial port"
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The ASB2305 board has two serial ports. Currently,
- only the first serial port is supported. This option
- chooses which port will be used to connect to a host
- running GDB."
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
- display "Diagnostic serial port"
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The ASB2305 board has two serial ports. Currently,
- only the first serial port is supported. This option
- chooses which port will be used for diagnostic output."
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
- display "Diagnostic serial port baudrates"
- flavor data
- legal_values 9600 19200 38400 57600 115200
- default_value 38400
- description "
- The ASB2305 debug serial port baud rate setting."
- }
-
- cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_RTSCTS {
+ cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_RTSCTS {
display "Diagnostic serial port RTS/CTS flow control"
flavor bool
default_value 0
description "
The ASB2305 debug serial port RTS/CTS flow control setting."
- }
+ }
+
+ cdl_option CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS {
+ display "ASB2305 has one comm channels."
+ flavor data
+ default_value 1
+ }
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
@@ -311,10 +278,12 @@ cdl_package CYGPKG_HAL_MN10300_AM33_ASB2
description "This option enables the conversion of the Redboot ELF
image to a binary image suitable for ROM programming."
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
}
}
}
Index: hal/mn10300/stb/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mn10300/stb/current/ChangeLog,v
retrieving revision 1.8
diff -u -p -5 -r1.8 ChangeLog
--- hal/mn10300/stb/current/ChangeLog 6 Aug 2002 16:00:19 -0000 1.8
+++ hal/mn10300/stb/current/ChangeLog 19 Nov 2002 13:52:19 -0000
@@ -1,5 +1,12 @@
+2002-11-19 Mark Salter <msalter@redhat.com>
+
+ * cdl/hal_mn10300_am33_stb.cdl: Remove virtual vector comm support.
+ Add options to select AM33 serial ports for comm channels. Add
+ override for default processor clock frequency.
+ * src/ser_stb.c: Removed.
+
2002-08-06 Gary Thomas <gary@chez-thomas.org>
2002-08-06 Motoya Kurotsu <kurotsu@allied-telesis.co.jp>
* src/ser_stb.c: I/O channel data can't be constant - contains
timeout information which can be changed.
Index: hal/mn10300/stb/current/cdl/hal_mn10300_am33_stb.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mn10300/stb/current/cdl/hal_mn10300_am33_stb.cdl,v
retrieving revision 1.5
diff -u -p -5 -r1.5 hal_mn10300_am33_stb.cdl
--- hal/mn10300/stb/current/cdl/hal_mn10300_am33_stb.cdl 23 May 2002 23:04:07 -0000 1.5
+++ hal/mn10300/stb/current/cdl/hal_mn10300_am33_stb.cdl 19 Nov 2002 13:52:19 -0000
@@ -57,16 +57,14 @@ cdl_package CYGPKG_HAL_MN10300_AM33_STB
include_dir cyg/hal
description "
The STB HAL package should be used when targetting the
actual hardware for the AM33 STB evaluation board."
- compile hal_diag.c plf_stub.c plf_misc.c ser_stb.c
+ compile hal_diag.c plf_stub.c plf_misc.c
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
- implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
- implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
requires CYGSEM_HAL_UNCACHED_FLASH_ACCESS == 1;
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_mn10300_am33.h>"
@@ -147,31 +145,34 @@ cdl_package CYGPKG_HAL_MN10300_AM33_STB
default_value 38400
description "
This option controls the baud rate used for the GDB connection."
}
+ cdl_option CYGSEM_HAL_AM33_PLF_USES_SERIAL0 {
+ display "ASB2303 uses AM33 SERIAL0"
+ flavor bool
+ default_value 1
+ description "
+ Enable this option if AM33 SERIAL0 is to be used as a virtual vector
+ communications channel."
+ }
+
+ cdl_option CYGSEM_HAL_AM33_PLF_USES_SERIAL1 {
+ display "ASB2303 uses AM33 SERIAL1"
+ flavor bool
+ default_value 1
+ description "
+ Enable this option if AM33 SERIAL1 is to be used as a virtual vector
+ communications channel."
+ }
+
# Real-time clock/counter specifics
- cdl_component CYGNUM_HAL_RTC_CONSTANTS {
- display "Real-time clock constants."
- flavor none
-
- cdl_option CYGNUM_HAL_RTC_NUMERATOR {
- display "Real-time clock numerator"
- flavor data
- calculated 1000000000
- }
- cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
- display "Real-time clock denominator"
- flavor data
- calculated 100
- }
- cdl_option CYGNUM_HAL_RTC_PERIOD {
- display "Real-time clock period"
- flavor data
- calculated 303750
- }
+ cdl_option CYGHWR_HAL_MN10300_PROCESSOR_OSC_DEFAULT {
+ display "Processor clock rate"
+ calculated 30375000
+ flavor data
}
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
@@ -244,39 +245,10 @@ cdl_package CYGPKG_HAL_MN10300_AM33_STB
flavor data
default_value 25
description "
This option determines the number of breakpoints supported by the HAL."
}
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
- display "Number of communication channels on the board"
- flavor data
- calculated 1
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
- display "Debug serial port"
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The STB board has two serial ports. Currently,
- only the first serial port is supported. This option
- chooses which port will be used to connect to a host
- running GDB."
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
- display "Diagnostic serial port"
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The STB board has two serial ports. Currently,
- only the first serial port is supported. This option
- chooses which port will be used for diagnostic output."
- }
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define