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ARM926ej Cache and MMU Supprt
- From: Jerin Jacob <Jerin dot Jacob at maxim-ic dot com>
- To: "ecos-discuss at sourceware dot org" <ecos-discuss at sourceware dot org>
- Date: Wed, 21 Apr 2010 15:29:03 -0500
- Subject: [ECOS] ARM926ej Cache and MMU Supprt
Hi All,
We are in the process of porting eCos on arm926ej based SoC.
We have almost completed the HAL porting.
However, When try to enable MMU and D-cache.
We are facing an issue while running kache1 test case.
The kcache1 test case fails when running with D-cache on and I-cache off( undefined instruction
exception).All other modes like D-cache on and I-cache on work as expected.
In fact, All eCos test cases are passing with D and I cache enable at start-up.
It would be really great, if some throw some lights to this problem.
Few questions
1)Has any one verified eCos port with arm926ej ?
2)Can we re-use arm9 code exist for MMU static table creation and Cache operations for arm926j
3) We are using eCos V3.0, Any specific patches is required to bring up cache on arm926ej for eCos ?
Implementation details:
------------------------------
1) Followed MMU table creation and Cache operations code from eCos arm9
2) Changed default eCos arm D-cache size to 16kb from 8kb
3) Here is the MMU static entries
X_ARM_MMU_SECTION(0x000,0x000,MG3500_SDRAM_SIZE_IN_MB,ARM_CACHEABLE,ARM_BUFFERABLE,ARM_ACCESS_PERM_RW_RW);//SDRAM(Bridge 1)
X_ARM_MMU_SECTION(0xC00,0xC00,MG3500_SDRAM_SIZE_IN_MB,ARM_UNCACHEABLE,ARM_UNBUFFERABLE,ARM_ACCESS_PERM_RW_RW);//SDRAM( Bridge 2)
X_ARM_MMU_SECTION(0x800,0x800,128,ARM_UNCACHEABLE,ARM_UNBUFFERABLE,ARM_ACCESS_PERM_RW_RW);//AHB_PERIPH
X_ARM_MMU_SECTION(0x882,0x882,1,ARM_UNCACHEABLE,ARM_UNBUFFERABLE,ARM_ACCESS_PERM_RW_RW);//APB
X_ARM_MMU_SECTION(0x900,0x900,2,ARM_UNCACHEABLE,ARM_UNBUFFERABLE,ARM_ACCESS_PERM_RW_RW);//GMAC,USB
Thanks in Advance,
Jerin.
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