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Re: cache configuration for 946es
- From: "Yin Wen Chao (尹文超)" <yinwenchao at vimicro dot com>
- To: "ecos-discuss" <ecos-discuss at ecos dot sourceware dot org>
- Date: Tue, 5 Dec 2006 23:34:59 +0800
- Subject: Re: [ECOS] cache configuration for 946es
- Reply-to: yinwenchao at vimicro dot com
Hi,Sinan KAYA
Maybe a bug in macro HAL_DCACHE_SYNC() definition for CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX.
Try the following modifying in packages/hal/arm/arm9/var/<VERSION>/include/hal_cache.h:
1. Add a macro, CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_4WAYS
2. Add a HAL_DCACHE_SYNC() definition for CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_4WAYS
Furthermore, confirm the definition of HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) correspond to
the region WRITEBACK/WRITETHU attribute in the initialization of Memory Protection Unit.
---
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM946ES)
# define HAL_ICACHE_SIZE 0x2000
# define HAL_ICACHE_LINE_SIZE 32
# define HAL_ICACHE_WAYS 4
# define HAL_ICACHE_SETS
(HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0x1000
# define HAL_DCACHE_LINE_SIZE 32
# define HAL_DCACHE_WAYS 4
# define HAL_DCACHE_SETS
(HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
//# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_4WAY
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x400
#elif defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_4WAYS)
#define HAL_DCACHE_SYNC() \
CYG_MACRO_START \
cyg_uint32 _tmp1, _tmp2; \
asm volatile ( \
"mov %0, #0;" \
"1: " \
"mov %1, #0;" \
"2: " \
"orr r0,%0,%1;" \
"mcr p15,0,r0,c7,c14,2;" /* clean index in DCache */ \
"add %1,%1,%2;" \
"cmp %1,%3;" \
"bne 2b;" \
"add %0,%0,#0x40000000;" /* get to next index, only for 4way cache */ \
"cmp %0,#0;" \
"bne 1b;" \
"mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
: "=r" (_tmp1), "=r" (_tmp2) \
: "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP), \
"I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT) \
: "r0" /* Clobber list */ \
); \
CYG_MACRO_END
#elif defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
#define HAL_DCACHE_SYNC() \
CYG_MACRO_START \
cyg_uint32 _tmp1, _tmp2; \
asm volatile ( \
"mov %0, #0;" \
"1: " \
"mov %1, #0;" \
"2: " \
"orr r0,%0,%1;" \
"mcr p15,0,r0,c7,c14,2;" /* clean index in DCache */ \
"add %1,%1,%2;" \
"cmp %1,%3;" \
"bne 2b;" \
"add %0,%0,#0x04000000;" /* get to next index */ \
"cmp %0,#0;" \
"bne 1b;" \
"mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
: "=r" (_tmp1), "=r" (_tmp2) \
: "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP), \
"I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT) \
: "r0" /* Clobber list */ \
); \
CYG_MACRO_END
-----------------------------------
>Hi again,
>? checked the values from cache type register of arm
>?t says
>
>icache_Asc =2 -> four way associative
>?cache_Sz = 4 ->8kb
>?cache_pl = 2 -> 8 words per line
>
>dcache_Asc =2 -> four way associative
>dcache_Sz = 3 ->4kb
>dcache_pl = 2 -> 8 words per line
>
>
># define HAL_ICACHE_SIZE 0x2000
># define HAL_ICACHE_LINE_SIZE 32
># define HAL_ICACHE_WAYS 4
># define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
>
># define HAL_DCACHE_SIZE 0x1000
># define HAL_DCACHE_LINE_SIZE 32
># define HAL_DCACHE_WAYS 4
># define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
>
>How is the relationship between HAL_ICACHE_LINE_SIZE and 8 words per line. Is the unit of HAL_ICACHE_LINE_SIZE bytes ?
>Sinan.
>
>-----Original Message-----
>From: Yin Wen Chao (尹文超) [mailto:yinwenchao@vimicro.com]
>Sent: Tuesday, December 05, 2006 11:12 AM
>To: Sinan KAYA
>Subject: Re: [ECOS] cache configuration for 946es
>
>Hi,Sinan KAYA
>
> You should compare those cache information from the document you mentioned
>with those from the ARM you have.
>
>Reference:
>http://www.arm.com/pdfs/DDI0155A_946ES.pdf
>
> You can access the cache type register by reading CP15 register c0 with the Opcode_2
>field set to 1. For example:
> MRC p15, 0, <Rd>, c0, c0, 1; returns cache details
>
>-----------------------------------
>>Hi,
>>i have a 946es variant and i'm unable to pass kcache2 test even though
>>other cache tests, cache and kcache1 pass.
>>
>>I googled a little bit. Previous posts say that this test is designed to
>>find misconfigurations. So, i assume i have a misconfiguration. The
>>document of board tells me that i have 8 kb instruction cache, 4kb data
>>cache with four way associative set and 1024 byte segments.
>>
>>Each segment consists of 32 lines with 32 ( 8 x 4 bytes) bytes.
>>
>>and here is my configuration
>>
>>#elif defined(CYGPKG_HAL_ARM_ARM9_ARM946ES)
>>
>># define HAL_ICACHE_SIZE 0x2000
>># define HAL_ICACHE_LINE_SIZE 32
>># define HAL_ICACHE_WAYS 4
>># define HAL_ICACHE_SETS
>>(HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
>>
>># define HAL_DCACHE_SIZE 0x1000
>># define HAL_DCACHE_LINE_SIZE 32
>># define HAL_DCACHE_WAYS 4
>># define HAL_DCACHE_SETS
>>(HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
>>
>># define HAL_WRITE_BUFFER 32
>># define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
>># define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
>># define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x400
>>
>>
>>can anybody see a mistake?
>>
>>--
>>Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
>>and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
>-----------------------------------