[ECOS] Re: PCI driver development for NI-DAQ PCI-DIO-96 card

[Gary Thomas <gary at mlbassoc dot com>]

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On Fri, 2005-12-02 at 10:22 +0500, Khateeb wrote:
> --
> Abdullah <abdullahkhateeb@gmail.com>
> College Senior
> 
> We are trying to write a PCI device driver for NI-DAQ PCI-DIO-96 card
> using eCos.
> The target platform is intel P4 processor/mother-board.
> The host system is an intel pentium P3 PC running windows XP.
> 
> I have successfully detected the device using the device-id.
> The device info structure read from the PCI configuration space header
> region is
> 
> vendor ID=0x1093
> device ID=0x0160   
> command register=0x117 
> status register = 0x280
> class + revision = 0xff000000
> cache line size =0x10
> latency timer =0x10
> Built-in Self-Test =0x0
> Num of BAR=0x2 
> Base_Address[0]=0xfcfde000
> Base_Address[1]=0xfcfdf000
> Base_Size[0]=0x0
> Base_Size[1]=0x0
> Base_Map[0]=0xfcfde000
> Base_Map[1]=0xfcfdf000
> 
> I am assuming that the Base_Address[0] corresponds to BAR(0) and
> Base_Address[1] corresponds to BAR(1). I have tried to write on these
> registers through 'HAL_WRITE_UINT32' command but i haven't been
> successful in that since reading those registers again gives the same
> previous values of 
> Base_Address[0]=0xfcfde000
> Base_Address[1]=0xfcfdf000
> using the read command which is 'HAL_READ_UINT32'.

Does your device actually respond to 32 bit accesses when using BAR(1)?
Your code (below) doesn't look obviously wrong to me, but you need to
know the characteristics of the device "behind" the PCI interface.

> 
> The basic probelm lies in configuring the base address and finding an
> appropriate offset; which so far i have not been able to do so. I have
> taken help from the PCI sample programs 'pci1.c' and 'pci2.c'.
> 
> 
> #include <pkgconf/system.h>
> #include <cyg/hal/hal_io.h>
> 
> #include <cyg/infra/diag.h>             // diag_printf
> #include <cyg/infra/testcase.h>         // test macros
> #include <cyg/infra/cyg_ass.h>          // assertion macros
> 
> // Package requirements
> #if defined(CYGPKG_IO_PCI) && defined(CYGPKG_KERNEL) && defined
> (CYGPKG_ISOINFRA)
> 
> #include <pkgconf/kernel.h>
> #include <pkgconf/io_pci.h>
> #include <cyg/io/pci.h>
> #include <cyg/hal/hal_arch.h>
> #include <string.h>
> 
> // Package option requirements
> #if defined(CYGFUN_KERNEL_API_C) && defined(CYG_PCI_PRESENT)
> 
> #include <cyg/kernel/kapi.h>
> 
> // If the target has limited memory resources, undef the below to
> // avoid inclusion of the big PCI code tables.
> //
> // The header file is created from http://www.yourvote.com/pci
> // maintained by Jim Boemler (jboemler@halcyon.com).
> //
> // If you have PCI devices not listed in this list, please consider
> // registering the codes in the database. 
> #define USE_PCI_CODE_LIST
> 
> #ifdef USE_PCI_CODE_LIST
> #include "pcihdr.h"
> #endif
> 
> // You may want to use this code to do some simple testing of the
> // devices on the PCI bus. By enabling the below definition, the
> // devices will get PCI IO and MEM access activated after
> configuration
> // so you can play with IO registers and display/set contents of MEM. 
> #define ENABLE_PCI_DEVICES
> 
> unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL];
> cyg_thread thread_data;
> cyg_handle_t thread_handle;
> 
> void
> pci_test( void )
> {
>     cyg_pci_device dev_info;
>     cyg_pci_device_id devid;
>     CYG_ADDRWORD irq;
>     cyg_uint32 * mitebase;
>     cyg_uint32 *tempAddr;
>     
>     cyg_uint16 cardbase; 
>     
>     CYG_PCI_ADDRESS64 mem_base0=0xEEEEE000;
>     CYG_PCI_ADDRESS64 mem_base1=0xEEEEF000;
>     
>     cyg_uint8 bus;
>     cyg_uint8 *next_bus;     
>     
>     int i;
>     int count=0;
>     cyg_uint8 data_read[40]; 
>     cyg_uint8 tempVal;
> #ifdef USE_PCI_CODE_LIST
>     cyg_bool no_match = false;
>     cyg_uint16 vendor, device;
>     cyg_uint8  bc, sc, pi;
>     PCI_VENTABLE* vtbl;
>     PCI_DEVTABLE* dtbl;
>     PCI_CLASSCODETABLE* ctbl; 
> #endif
>  cyg_pci_init();
>  devid=133120; // The device ID used for NI-DAQ PCI-DIO-96
> 
>  cyg_pci_get_device_info(devid, &dev_info); 
>  cyg_pci_set_device_info(devid, &dev_info);
>  
>   
>         if (cyg_pci_configure_device(&dev_info)) 
>         {         
>   #ifdef ENABLE_PCI_DEVICES 
>                     cyg_uint16 cmd;
>                     cyg_pci_read_config_uint16(dev_info.devid,
> CYG_PCI_CFG_COMMAND, &cmd);
>                     cmd |= CYG_PCI_CFG_COMMAND_IO|
> CYG_PCI_CFG_COMMAND_MEMORY;
>                     cyg_pci_write_config_uint16(dev_info.devid,
> CYG_PCI_CFG_COMMAND, cmd);
>       
>       //diag_printf("\n Device IO and MEM access enabled
> \n");                                                
>   #endif
>         }
>         
>  // Writing data to the memory allocated to BAR[1]
>  //      Basically trying to access the devices registers so 
>  // that we can program the 8255 Chip.
>         for(i = 0; i <= 16; i++) 
>         {
>          HAL_WRITE_UINT8(dev_info.base_map[1]+i,0x20);
>          HAL_READ_UINT8(dev_info.base_map[1]+i,tempVal);
>          diag_printf(" count[%d]=%04x \n", i, tempVal);
>         }   
> }
> 
> void
> cyg_start(void)
> {
>     CYG_TEST_INIT();
>     cyg_thread_create(10,                     // Priority - just a
> number
>                       (cyg_thread_entry_t*)pci_test,    // entry
>                       0,                      // 
>                       "pci_thread",       // Name
>                       &stack[0],              // Stack
>                       CYGNUM_HAL_STACK_SIZE_TYPICAL,    // Size
>                       &thread_handle,         // Handle 
>                       &thread_data            // Thread data structure
>         );
>     cyg_thread_resume(thread_handle);
>     cyg_scheduler_start();
> }
> 
> #endif
> #endif
> 
> Any help would be much appreciated.
> Regards,
> Abdullah
> 
-- 
Gary Thomas <gary@mlbassoc.com>


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