Re: [ECOS] When to enable the IE bit of MIPS status register in eCos?

["Michael Anburaj" <embeddedeng at hotmail dot com>]

Hi,

The following line of code at HAL_THREAD_INIT_CONTEXT() of 
hal/mips/arch/current/include/ hal_arch.h enables the IE bit of the SR image 
(in the prepared context):

(_regs_)->sr  = 0x00000001;                       /* SR = ls 3 bits only    
*/      \

This prepared SR image gets to the STATUS register, when loading the context 
of the ecos Application to be run from Redboot, look at the following code 
in hal_thread_load_context() of hal/mips/arch/current/src/context.s:

	lw	a2,mipsreg_sr(sp)		# A2 = saved SR
	lsp	sp,sp			# SP = saved SP

	hal_cpu_int_merge a2			# Merge with current SR


So when the new ecos RAM application is booted using Redboot (in ROM) the IE 
bit get enabled automaticaly.

I just took a quick look & giving you this piece of info. (I may be wrong! 
:-) )



> From: kjlin@aviqtech.com
> To: ecos-discuss@sources.redhat.com
> Subject: [ECOS] When to enable the IE bit of MIPS status register in eCos?
> Date: Wed, 9 Jul 2003 14:27:08 +0800
>
> Hi all,
>
> I am quite new in the eCos world.
> I tried to port eCos to my MIPS platform, but i got a question.
> In what stage will the eCos kernel enable the IE bit (global interrupt
> enable) of the STATUS register?
> Or i have to do it in cyg_user_start() function by myself?
> Will it make the system unstable if i enable the IE bit early in the
> hal_platform_init() function?
> Any hints are appreciated.
> Thanks,
>
> KJ
>
>
> --
> Before posting, please read the FAQ: http://sources.redhat.com/fom/ecos
> and search the list archive: http://sources.redhat.com/ml/ecos-discuss

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