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RE: ARM - RAM region at other address than 0


Hi.
we already get this problem with is ARM processor that has internal ROM 0
(no way to use external logic)
to make the thing work, we change 2 things :
- change the memory mapping files .ldi & .mlt to map the section
'fixed_vectors' in RAM
for the file ldi, it something like
SECTIONS
{
...
SECTION_fixed_vectors (ram, 'somewhere', LMA_EQ_VMA)
...
SECTIONS_END
}
- copy the content of '.vectors' in '.hal_vsr_table' in your
PLATFORM_SETUP1 macro
ldr r0, .vectors
ldmia r0,{r1, r2, r3, r4, r5, r6, r7, r8}
ldr r0, .hal_vsr_table
stmia r0,{r1, r2, r3, r4, r5, r6, r7, r8}


it works like this for a long time Arnaud

hello,

> On Mon, 2003-05-19 at 14:33, Grant Edwards wrote:
> > On Mon, May 19, 2003 at 04:11:38PM -0400, Doyle, Patrick wrote:
> >
> > > I glanced at the '5471 data manual and I don't see the
> > > "mechanism for swapping ROM and SDRAM at address 0" that I was
> > > expecting to see... Hmmm.... Perhaps you should ask TI about
> > > this.  eCos really likes to see interrupt vectors in RAM.
> >
> > At one point I had a hacked version of vectors.S that worked
> > with ROM at 0.  It did the "double vector" thing (not very
> > pretty).  After tiring of the requirement to maintain my own
> > vectors.S, I finally swapped ROM/RAM -- life is easier that
> > way.
> >
> > If the 5471 doesn't have some sort of software-controlled
> > chip-select logic, then when you lay out your board you should
> > add a couple gates to allow two of the chip selects to be
> > swapped.

we will use a SDRAM as RAM. swapping chip selects works when you have a SRAM
and Flash. I don't think it would work with SDRAM because the processors
won't generate the SDRAM specific control signals when it expects to
read/write an asynchronous memory.

> However, if anyone wants to experiment
> with Grant's approach (from *long* ago), I still have the patches
> that he sent me for this :-)

yeah, I want it.


thanks.


Regards,
Willy


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