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Pb with hal_cache.h for the ARM9 variants
- From: Tristan Corcelle <tco at teamlog dot com>
- To: ecos-discuss at sources dot redhat dot com
- Date: Thu, 13 Mar 2003 17:41:06 +0100
- Subject: [ECOS] Pb with hal_cache.h for the ARM9 variants
- Organization: Teamlog
Hi all,
Can anybody help me? I'm porting eCos on a ARM946E-S board and I have to
integrate this core in the cache memory driver
(packages/hal/arm/arm9/var/current/include/hal_cache.h).
After an analyse of the existing code, I found something strange.
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM922T)
# define HAL_ICACHE_SIZE 0x2000
# define HAL_ICACHE_LINE_SIZE 32
# define HAL_ICACHE_WAYS 64
# define HAL_ICACHE_SETS
(HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0x2000
# define HAL_DCACHE_LINE_SIZE 32
# define HAL_DCACHE_WAYS 64
# define HAL_DCACHE_SETS
(HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 64
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x80
[...]
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T)
# define HAL_ICACHE_SIZE 0x1000
# define HAL_ICACHE_LINE_SIZE 16
# define HAL_ICACHE_WAYS 4
# define HAL_ICACHE_SETS
(HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0x1000
# define HAL_DCACHE_LINE_SIZE 16
# define HAL_DCACHE_WAYS 4
# define HAL_DCACHE_SETS
(HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 32
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x10
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x40
Here, there are two cores: ARM922T et ARM940T.
For the ARM922T HAL_DCACHE_WAYS refers to the number of row in each seg of the
DCache memory.
For the ARM940T HAL_DCACHE_WAYS refers to the number of seg.
In both cases, there are 64 rows in each seg and there are 4 seg.
Is there any error? if not, could anybody explain me the difference?
Thanks,
Tristan
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