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about layout of code
- From: zhlg_shuhan <zhlg_shuhan at sina dot com>
- To: Iztok Zupet <iz at vsr dot si>
- Cc: ecos-discuss at sources dot redhat dot com
- Date: Sat, 06 Jul 2002 12:14:12 +0800
- Subject: [ECOS] about layout of code
hi ,sir!
I have several questions to consult you:
1: when a exception occured,exception vector code:
_exception_\name:
mtspr SPRG1,r3 # stas
mtspr SPRG2,r4
mtspr SPRG3,r5
mfcr r4 # stash CR
li r5,__exception_\name@L # load low half
srwi r5,r5,6 # shift right by
lwi r3,hal_vsr_table # table base
lwzx r3,r3,r5 # address of vsr
mflr r5 # save link register
mtlr r3 # put vsr address in
li r3,__exception_\name@L # reload low half of
blr # go to common code
was executed,but in seccession,"blr" will go to exception common code:cyg_hal_default_exception_vsr
I don't know how blr branchs to "cyg_hal_default_exception_vsr's code" because no evidence to show cyg_hal_default_exception_vsr code was placed into hal_vsr_table,right?
2:when a exeption occurs,only SRR0(pc),SRR1(MSR) were saved automatically in ppcxxx?
3:about assembler directives:
i found several ".text" directives with zero subsection according its explanation,but i do not know how these codes with ".text" will be layout? for example:
.text
_start
...
and
.text
cyg_hal_default_exception_vsr:
tks®ards
zhlg
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