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Mem maps and mmu for iq80310


The mlt_arm_iq80310_*.h files probably calculate the Heap sizes
incorrectly. Probably the caculations are based on the assumption that
RAM always starts at Address 0??
I was also wondering why the mmu page tables are being setup so that the
first 1MB of SDRAM is cached and not buffered, while the rest is cached
and buffered. I did not see any difference in the way the first 1MB is
used.

-Thanks
Ashwin.
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