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[Bug 1001480] Generic 16x5x driver: inverted chronology inpc_serial_start_xmit(): superfluous ISR/DSR run


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--- Comment #1 from Bernard Fouchà <bernard.fouche@kuantic.com> 2012-02-11 13:17:51 GMT ---
For the sake of completeness: NS/TI datasheet says:

"B. The transmitter FIFO empty indications will be delayed 1
character time minus the last stop bit time whenever the
following occurs: THRE=1 and there have not been at
least two bytes at the same time in the transmit FIFO,
since the last THRE=1. The first transmitter interrupt af-
ter changing FCR0 will be immediate, if it is enabled."

So the behavior I observed is dependent of the processing speed of the MCU and
the UART speed: if the MCU clocks much faster than the UART speed, then the MCU
may have time to fill the FIFO even if THRE (XMIT interrupt) is set. However
always filling the FIFO before enabling THRE as I proposed gives the same
result and in a deterministic manner.

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