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[Bug1001300] problÃme de commutation des taches


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--- Comment #6 from Christophe Coutand <ecos@hotmail.co.uk> 2011-08-06 18:22:20 BST ---
When browsing the MIPS32 architecture of SoClib, i can't see that the
coprocessor 0 count / compare registers are triggering interrupts. You should
check that by asking on the SoClib mailing list.

As a workaround, you can implement the eCos RTC clock using the vci-xicu timer
instead.

BTW, could you provide the ecos.ecc you are using to build eCos?

Christophe

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