[Bug 1001145] Cache handling crashes ARM920T with MMU enabled

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--- Comment #2 from Stanislav Meduna <stano@meduna.org> 2011-02-09 10:25:13 GMT ---
No it does not help. I think I tried it before too, now I tested it again to
make sure.

There is indeed some connection with the interrupts, I experimented and it
makes a lot of difference how often the timer interrupt is ticking; but this
can also be due to different code paths across threads being taken and
resulting different content of the D-cache, so it is not 100%.

You are right that the problem first manifested itself using a flash (it was
quite a challenge to hunt a bug like this down to the single line),
specifically CYKPKG_DEVS_FLASH_SST_39VFXX. The macros are pulled in via
io/flash/current/src/flash.c - all current from the CVS.

What do you mean by using the new flash infrastructure? I need a filesystem on
top of a NOR flash and this is what gets configured in that case, or am I
missing something?

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