Re: Coldfire/M68K 32 bit RAM access?

["David Brown" <david at westcontrol dot com>]

----- Original Message -----
From: "Alan Cudmore" <Alan.P.Cudmore@nasa.gov>
To: <crossgcc@sources.redhat.com>
Sent: Friday, October 17, 2003 10:00 PM
Subject: Coldfire/M68K 32 bit RAM access?


> I'm working on a custom embedded Coldfire processor board that has 512K of
> SRAM on it.
> This SRAM only allows 32 bit reads and writes, and the lower two address
> bits do not connect to the coldfire.
> There is nothing on the board to try to compensate for this either. I had
> worked with other boards that had an EDAC that would do a
read-modify-write
> operation for 8 or 16 bit operations.
>

Are you sure you have only full 32-bit writes?  This would be very unusual -
every system I have seen has been able to write at the level of individual
bytes (I'm not sure, but I believe that's what the term "byte" actually
means, even though most of us think it is synonymous to "octet").  Ansi C,
and (probably) all C compilers expect to be able to read and write data at
the level of a "char" - on the horrible DSP I once used which had 16-bit
minimum access, a char was 16 bits wide.

On systems with 32-bit (or wider) databuses, the usual procedure is to have
byte select signals to the RAM chips.  Check the design for signals called
"BE0..3", "WE0..3", or similar.  These are used by the processor to indicate
which bytes out of the 32-bit word are to be written - the others are left
untouched.

mvh.

David


> Am I correct in thinking that GCC compiled code will not run on this?
>
> I see immediate problems when I move the stack from internal ( on chip )
> SRAM to this on-board SRAM.
>
> I tried the -malign-int option and that seems to help with the stack
> alignment, but I cant see how I could constrain GCC to never do anything
> other than 32 bit word accesses?
> Does this sound right?
>
> Thanks,
> Alan Cudmore
>
>
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