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On Tue, Dec 05, 2000 at 10:10:02AM +0100, Julien Ducourthial wrote:The exact behaviour seems to depend on the PPC model. I worked on a driver for AMD ethernet chip, for an in-house OS. There was no eieio in the code, but the registers were mapped with guarded and cache-inhibited mmu attributes. It ran flawlessly on a 603e board. But when we received newer boards with 604e cpu, the driver wasn't anymore working.
> Unfortunately there is no such thing on PowerPC, even when set as non-cached and
> guarded (the most conservative setting) you may get out of order accesses.Does this behaviour depend on the specific PPC CPU/MMU used? When working on
MPC860, setting IO spaces to non-cache/guarded (that was the term I was
looking for) worked fine without requiring eioio instructions throughout the
code.I guess I should re-read that chapter in the manual next week ...
cu
Michael
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Michael Schwingen, Ahornstrasse 36, 52074 Aachen------
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The problem was that the chip internal registers are accessed
through 2 registers (one for address, one for data), so when reading an
internal register you have to first write its adress then read the data.
Without eieio in between, the read is made ahead of the write (at least
on the 604e) and ... you do not really get the data expected.
-- Julien Ducourthial julien.ducourthial@detexis.thomson-csf.com LDB Dépt SIA, SBU ISA THOMSON-CSF DETEXIS
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