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We are using version 2.7.2 of GCC (Wind River supplies it as part of the Tornado environment. Wind River claims it is the best version if one is using C). We are seeing the following behavior on a PPC: We have a VME board used for I/O. When sending data, we fill a buffer on the board, and then write to a special location that tells the board the buffer is ready. The board then sets a bit saying that it is in the process of sending the data. We look for that bit to be cleared before we try to use the buffer again. The problem is that we have a loop that waits for the bit to be cleared, and then we immediately start putting the data in the buffer, and the PowerPC is writing the data before the bit is cleared. Using a VME bus analyzer, we see a number of reads (looking for the bit to be cleared), followed by "write, read, write, read" for a while, followed by the rest of the writes. Naturally, the locations we are talking about are declared volatile, so the compiler does not optimize the code, but the PowerPC has its own optimization in the form of pipelining, and it seems to be causing this problem. The question is, should the compiler be inserting an "eieio" instruction at the sequence points in the code, such as the end of the loop mentioned above? This PPC instruction tells the processor to hold off its pipelining. We have been inserting them in the code ourselves, but it is a bit of a pain to have to do it. Another question is, does anyone know if a later version of the compiler has fixed this problem? Roger Racine Draper Laboratory ------ Want more information? See the CrossGCC FAQ, http://www.objsw.com/CrossGCC/ Want to unsubscribe? Send a note to crossgcc-unsubscribe@sourceware.cygnus.com
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