Re: dni format description

[Jean-Marc Saffroy <jean-marc dot saffroy at joguin dot com>]

Hi Petronela,

Please post to only one instance of the cgen list, thank you.

On 08/05/2010 10:23 AM, Petronela Agache wrote:
> Hello,
> My name is Petronela, i would like to get more info about the format
> field from pmacros. For example the following insn is used in
> m32r.cpu:
> (dni addx "addx"
> 
>      ((PIPE OS) (IDOC ALU))
>      "addx $dr,$sr"
>      (+ OP1_0 OP2_9 dr sr)
>      (parallel ()
>                (set dr (addc dr sr condbit))
>                (set condbit (add-cflag dr sr condbit)))
>      ()
> 
> )
> What (+ OP1_0 OP2_9 dr sr) means ?

This is the format for this instruction.

It means that this particular instruction has 4 fields, of which 2
(OP1_0 and OP2_9) have a fixed value. It's only the layout of the
instruction, ie. which bits are constant (typically the instruction
opcode) and which are not (instruction operands).

Above the dni macro, you will find definitions for various instruction
fields. This instruction is a combination of 4 of those fields, which
cover exactly all the bits in the instruction.

> OP1_* and OP2_* are defined in the
> following way:
> (define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
> 
>   ("0" "1" "2" "3" "4" "5" "6" "7"
>    "8" "9" "10" "11" "12" "13" "14" "15")
> 
> )
> (define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
> 
>   ("0" "1" "2" "3" "4" "5" "6" "7"
>    "8" "9" "10" "11" "12" "13" "14" "15")
> 
> )

Yes, so OP1_0 means field f-op1 of an instruction, with constant value 0
for those bits. Same for OP2_9.

On the other hand, dr and sr are defined as fields which are to be
interpreted as register numbers.

> My understanding is that destination register is always R0 and source
> register is always R9 for this type of insn. Is this correct ? Does
> this not restrict the hardware usage ? Since this insn can be executed
> on all R* registers.

This is not correct. The actual semantic of the instruction is after the
format:

>      (parallel ()
>                (set dr (addc dr sr condbit))
>                (set condbit (add-cflag dr sr condbit)))
>      ()

This describes how instruction operands are used. In this example:
- add 3 registers: explicit operands dr and sr, and implicit operand condbit
- put the result in register dr
- compute the carry for the same addition
- put the carry in register condbit


Hope this helps.

Jean-Marc

> 
> Thank you
>