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variable width instructions
- From: David Carney <dfcarney at net-itech dot com>
- To: cgen at sources dot redhat dot com
- Date: Fri, 20 Dec 2002 17:57:54 -0500
- Subject: variable width instructions
- Organization: Net Integration Technologies
I'm trying to write a .cpu file for a simple, non-pipelined (CISC) chip. The
instructions and data are all 16 bits (little endian). Defining the
instruction fields was relatively straight forward, until I realised that
instructions involving 'immediate' datum are, in fact, 32 bits...
My question is: how I should go about defining the instruction fields for this
architecture? I.e. what value should I use for the "start" fields in
"(define-ifield ...)" for the msb so that instruction fields are compatible
for both 16-bit and (the effectively) 32-bit instructions (15 or 31) ?
My confusion stems from observing the line:
(dnf f-i32 "32 bit immediate" (SIGN-OPT) 16 32)
in fr30.cpu. Doesn't the "16 32" denote that the start of the opcode is at
bit 16, but the length is 32? For my ISA I need something equivalent to
"start" = -1, "length" = 16. How do I go about this?