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m32r port breakage

Yes, it's been ages since I've looked at the m32r port,
but it's the one I like to use when playing with things.
Hans-Peter has a patch he wants to go in and before it has my blessing
I want to play with it on a real port.

This patch breaks the m32r simulator.

2001-04-02  Ben Elliston  <>
	* sim-decode.scm (@prefix@_init_idesc_table): Compute tabsize
	using the size of the table and its elements.
	(-gen-decode-insn-globals): Define the idesc table's size to be
	the last instruction enum plus one, not @PREFIX@_INSN_MAX.
	* sim-model.scm (-gen-mach-defns): Define CPU_MAX_INSNS as the
	last instruction enum plus one, not @CPU@_INSN_MAX.

Why was @PREFIX@_INSN_MAX replaced with "last instruction enum plus one"?
For the m32r they're not the same thing.  The former takes into account
all the parallel semantic handlers causing this table in sim/m32r/decodex.c

static IDESC m32rxf_insn_data[M32RXF_INSN_SNC + 1];

to be smaller than it should be so that m32rxf_init_idesc_table
ends up clobbering memory beyond the table.

m32rxf_init_idesc_table (SIM_CPU *cpu)
  IDESC *id,*tabend;
  const struct insn_sem *t,*tend;
  int tabsize = sizeof (m32rxf_insn_data) / sizeof (IDESC);
  IDESC *table = m32rxf_insn_data;

  memset (table, 0, tabsize * sizeof (IDESC));

  /* First set all entries to the `invalid insn'.  */
  t = & m32rxf_insn_sem_invalid;
  for (id = table, tabend = table + tabsize; id < tabend; ++id)
    init_idesc (cpu, id, t);

  /* Now fill in the values for the chosen cpu.  */
  for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
       t != tend; ++t)
      init_idesc (cpu, & table[t->index], t);
      if (t->par_index != NOPAR)
>>>>	  init_idesc (cpu, &table[t->par_index], t);
>>>>	  table[t->index].par_idesc = &table[t->par_index];
      if (t->par_index != NOPAR)
>>>>	  init_idesc (cpu, &table[t->write_index], t);
>>>>	  table[t->par_index].par_idesc = &table[t->write_index];

  /* Link the IDESC table into the cpu.  */
  CPU_IDESC (cpu) = table;

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