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Disassembly of instruction with 4 bit opcode
- From: "Michael Chapman" <Michael dot Chapman at synopsys dot com>
- To: <cgen at sources dot redhat dot com>
- Date: Mon, 4 Nov 2002 13:19:28 +0100
- Subject: Disassembly of instruction with 4 bit opcode
I have now got the assembler working. However I still have a
little problem with disassembly which I do not understand.
The problem is with the "call" instructions which use only 4 bits
of the opcode using the remained for the address. Everything is
strictly little endian with the opcode always appearing in the
least significant 8 bits (or 4 bits in the case of call) of the
instruction.
When I dissassemble the following (listing output from the
assembler)
Dw32 GAS test1.asm page 1
1
2 0000 06100010 start: mov r1, #0x1000
3
4 0004 06302800 mov r3, #low(msg)
5 0008 56230000 l1: ldsb r2, (r3)0x0
6 000c 4120 cmp r2, #0
7 000e 8A0B beq finish
8 0010 CC000000 call putc
9 0014 2131 add r3, #1
10 0016 FAF8 bra l1
11
12 0018 A62000F0 putc: st r2, (r0)0xf000
13 001c 0620FFFF mov r2, #0xffff
I get
$ od -d test1.o
test1.o: file format elf32-dw32
Disassembly of section .text:
00000000 <start>:
0: 06 10 00 10 mov r1,#0x1000
4: 06 30 30 00 mov r3,#0x30
00000008 <l1>:
8: 56 23 00 00 ldsb r2,(r3)0x0
c: 41 20 cmp r2,#0x0
e: 8a 0f beq.s 2e <finish>
10: cc 00 *unknown*
12: 00 00 mov r0,r0
14: 21 31 add r3,#0x1
16: fa f8 bra.s 8 <l1>
00000018 <putc>:
18: a6 20 00 f0 st r2,(r0)0xf000
1c: 06 20 ff ff mov r2,#0xffff
The relevant bits of my cgen .cpu file are
(define-arch
(name dw32)
(comment "DW32")
(insn-lsb0? #t)
(machs dw32)
(isas dw32)
)
; Attributes
; Instruction set parameters.
(define-isa
; Name of the ISA.
(name dw32)
(comment "Basic DW32 instruction set")
; (Size of unknown instructions)
(default-insn-word-bitsize 16)
; Shortest instruction is 16 bits
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
; CPU family definitions.
(define-cpu
; CPU names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name dw32bf)
(comment "DW32 generic cpu")
(endian little)
(word-bitsize 32)
)
; Opcode fields
(dnf f-opcode "opcode" () 7 8)
(dnf f-call-opcode "call opcode" () 3 4)
; absolute, 28-bit (shifted 1 bit to right)
(df f-abs28 "abs28" (ABS-ADDR)
31 28 UINT
((value pc) (sra WI value (const 1)))
((value pc) (sll WI value (const 1))))
(dni call-abs28 "call abs28"
(UNCOND-CTI)
"call $abs28"
(+ (f-call-opcode #xc) abs28)
(set pc abs28)
()
)
Any ideas as to what my problem is?
Thanks for any help,
Mike Chapman