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Re: How to handle MIPS-like general register 0?
- To: Greg McGary <greg at mcgary dot org>
- Subject: Re: How to handle MIPS-like general register 0?
- From: Ben Elliston <bje at redhat dot com>
- Date: Fri, 19 Jan 2001 08:15:04 +1100 (EST)
- Cc: <cgen at sourceware dot cygnus dot com>
What's the recommended way of handling simulator semantics for a
general register zero that always reads as 0, and writes as bit-bucket
(as for MIPS)? Without CGEN support, I'll need to wrap a test for
reg# 0 as destination around the semantics of every insn that modifies
registers.
The clearest way (to the reader of the cpu description) is to define get/set
handlers for the register hardware:
(get (index)
(if (eq index 0)
(const SI 0)
(raw-reg h-gr index)))
In the case of MIPS, I suppose the action for setting r0 is to (nop).
Cheers, Ben