[PATCH v3 8/8] RISC-V: Fix testsuite failures
Marcus Comstedt
marcus@mc.pp.se
Sun Dec 27 14:53:35 GMT 2020
gas/
* testsuite/gas/riscv/li32.d: Accept bigriscv in addition
to littleriscv.
* testsuite/gas/riscv/li64.d: Likewise.
* testsuite/gas/riscv/lla32.d: Likewise.
* testsuite/gas/riscv/lla64.d: Likewise.
* testsuite/gas/riscv/march-ok-g2.d: Likewise.
* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
* testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise.
* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
ld/
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: (riscv_choose_ilp32_emul),
(riscv_choose_lp64_emul): Add them.
Call riscv_choose_ilp32_emul and riscv_choose_lp64_emul instead
of hardcoding elf32lriscv and elf64lriscv.
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call
riscv_choose_ilp32_emul instead of hardcoding elf32lriscv.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise.
* testsuite/ld-riscv-elf/c-lui-2.d: Likewise.
* testsuite/ld-riscv-elf/c-lui.d: Likewise.
* testsuite/ld-riscv-elf/call-relax.d: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise.
* testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition
to littleriscv.
* testsuite/ld-riscv-elf/weakref64.d: Likewise.
* testsuite/ld-scripts/empty-address-2a.d: xfail riscv64be.
* testsuite/ld-scripts/empty-address-2b.d: Likewise.
---
gas/testsuite/gas/riscv/li32.d | 2 +-
gas/testsuite/gas/riscv/li64.d | 2 +-
gas/testsuite/gas/riscv/lla32.d | 2 +-
gas/testsuite/gas/riscv/lla64.d | 2 +-
gas/testsuite/gas/riscv/march-ok-g2.d | 2 +-
gas/testsuite/gas/riscv/march-ok-g2_p1.d | 2 +-
gas/testsuite/gas/riscv/march-ok-g2p0.d | 2 +-
gas/testsuite/gas/riscv/march-ok-i2p0.d | 2 +-
.../gas/riscv/march-ok-i2p0m2_a2f2.d | 2 +-
.../gas/riscv/march-ok-nse-with-version.d | 2 +-
gas/testsuite/gas/riscv/march-ok-two-nse.d | 2 +-
.../ld-riscv-elf/attr-merge-arch-01.d | 2 +-
.../ld-riscv-elf/attr-merge-arch-02.d | 2 +-
.../ld-riscv-elf/attr-merge-arch-03.d | 2 +-
.../ld-riscv-elf/attr-merge-arch-failed-01.d | 2 +-
.../ld-riscv-elf/attr-merge-arch-failed-02.d | 2 +-
ld/testsuite/ld-riscv-elf/c-lui-2.d | 2 +-
ld/testsuite/ld-riscv-elf/c-lui.d | 2 +-
ld/testsuite/ld-riscv-elf/call-relax.d | 2 +-
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 39 +++++++++++++------
ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d | 2 +-
ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d | 2 +-
ld/testsuite/ld-riscv-elf/weakref32.d | 2 +-
ld/testsuite/ld-riscv-elf/weakref64.d | 2 +-
ld/testsuite/ld-scripts/empty-address-2a.d | 2 +-
ld/testsuite/ld-scripts/empty-address-2b.d | 2 +-
26 files changed, 53 insertions(+), 36 deletions(-)
diff --git a/gas/testsuite/gas/riscv/li32.d b/gas/testsuite/gas/riscv/li32.d
index ff0827dde9..947ea4f754 100644
--- a/gas/testsuite/gas/riscv/li32.d
+++ b/gas/testsuite/gas/riscv/li32.d
@@ -1,7 +1,7 @@
#as: -march=rv32ic -mabi=ilp32
#objdump: -dr
-.*: file format elf32-littleriscv
+.*: file format elf32-(little|big)riscv
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/li64.d b/gas/testsuite/gas/riscv/li64.d
index 54213031cc..498b2e513d 100644
--- a/gas/testsuite/gas/riscv/li64.d
+++ b/gas/testsuite/gas/riscv/li64.d
@@ -1,7 +1,7 @@
#as: -march=rv64ic -mabi=lp64
#objdump: -dr
-.*: file format elf64-littleriscv
+.*: file format elf64-(little|big)riscv
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d
index ab766b4e3b..9d87562906 100644
--- a/gas/testsuite/gas/riscv/lla32.d
+++ b/gas/testsuite/gas/riscv/lla32.d
@@ -1,7 +1,7 @@
#as: -march=rv32i -mabi=ilp32
#objdump: -dr
-.*: file format elf32-littleriscv
+.*: file format elf32-(little|big)riscv
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/lla64.d b/gas/testsuite/gas/riscv/lla64.d
index 7848eecdfb..c3b9581862 100644
--- a/gas/testsuite/gas/riscv/lla64.d
+++ b/gas/testsuite/gas/riscv/lla64.d
@@ -1,7 +1,7 @@
#as: -march=rv64i -mabi=lp64
#objdump: -dr
-.*: file format elf64-littleriscv
+.*: file format elf64-(little|big)riscv
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/march-ok-g2.d b/gas/testsuite/gas/riscv/march-ok-g2.d
index 38541ad6a6..7c92bc8bcb 100644
--- a/gas/testsuite/gas/riscv/march-ok-g2.d
+++ b/gas/testsuite/gas/riscv/march-ok-g2.d
@@ -2,4 +2,4 @@
#objdump: -dr
#source: empty.s
-.*: file format elf32-littleriscv
+.*: file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-g2_p1.d b/gas/testsuite/gas/riscv/march-ok-g2_p1.d
index cd9e127e66..da2247c9d9 100644
--- a/gas/testsuite/gas/riscv/march-ok-g2_p1.d
+++ b/gas/testsuite/gas/riscv/march-ok-g2_p1.d
@@ -2,4 +2,4 @@
#objdump: -dr
#source: empty.s
-.*: file format elf32-littleriscv
+.*: file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-g2p0.d b/gas/testsuite/gas/riscv/march-ok-g2p0.d
index b439314ccf..a11d55e499 100644
--- a/gas/testsuite/gas/riscv/march-ok-g2p0.d
+++ b/gas/testsuite/gas/riscv/march-ok-g2p0.d
@@ -2,4 +2,4 @@
#objdump: -dr
#source: empty.s
-.*: file format elf32-littleriscv
+.*: file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-i2p0.d b/gas/testsuite/gas/riscv/march-ok-i2p0.d
index eb8309c7e2..e413e09f88 100644
--- a/gas/testsuite/gas/riscv/march-ok-i2p0.d
+++ b/gas/testsuite/gas/riscv/march-ok-i2p0.d
@@ -2,4 +2,4 @@
#objdump: -dr
#source: empty.s
-.*: file format elf32-littleriscv
+.*: file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d b/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d
index 6658417b0f..11960ba5bf 100644
--- a/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d
+++ b/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d
@@ -2,4 +2,4 @@
#objdump: -dr
#source: empty.s
-.*: file format elf32-littleriscv
+.*: file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-nse-with-version.d b/gas/testsuite/gas/riscv/march-ok-nse-with-version.d
index bdca7fb18d..8e2110cef4 100644
--- a/gas/testsuite/gas/riscv/march-ok-nse-with-version.d
+++ b/gas/testsuite/gas/riscv/march-ok-nse-with-version.d
@@ -2,4 +2,4 @@
#objdump: -dr
#source: empty.s
-.*: file format elf32-littleriscv
+.*: file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-two-nse.d b/gas/testsuite/gas/riscv/march-ok-two-nse.d
index e78cf9dd09..8cdf316f04 100644
--- a/gas/testsuite/gas/riscv/march-ok-two-nse.d
+++ b/gas/testsuite/gas/riscv/march-ok-two-nse.d
@@ -2,4 +2,4 @@
#objdump: -dr
#source: empty.s
-.*: file format elf32-littleriscv
+.*: file format elf32-(little|big)riscv
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index 5baaba4c16..c148cdbc4f 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -1,7 +1,7 @@
#source: attr-merge-arch-01a.s
#source: attr-merge-arch-01b.s
#as:
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
#readelf: -A
Attribute Section: riscv
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index a7d79a1ea2..bc0e0fd138 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -1,7 +1,7 @@
#source: attr-merge-arch-02a.s
#source: attr-merge-arch-02b.s
#as:
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
#readelf: -A
Attribute Section: riscv
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index d46dee808d..374a043c69 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -1,7 +1,7 @@
#source: attr-merge-arch-03a.s
#source: attr-merge-arch-03b.s
#as:
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
#readelf: -A
Attribute Section: riscv
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
index 4b312388f7..669a139206 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
@@ -1,7 +1,7 @@
#source: attr-merge-arch-failed-01a.s
#source: attr-merge-arch-failed-01b.s
#as: -march-attr
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
#warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0
#readelf: -A
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
index 880ee15473..3f4935df54 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
@@ -3,7 +3,7 @@
#source: attr-merge-arch-failed-02c.s
#source: attr-merge-arch-failed-02d.s
#as: -march-attr
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
#warning: .*mis-matched ISA version 3.0 for 'i' extension, the output version is 2.0
#warning: .*mis-matched ISA version 3.0 for 'm' extension, the output version is 2.0
#warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0
diff --git a/ld/testsuite/ld-riscv-elf/c-lui-2.d b/ld/testsuite/ld-riscv-elf/c-lui-2.d
index 622c0f7a31..d363da10c3 100644
--- a/ld/testsuite/ld-riscv-elf/c-lui-2.d
+++ b/ld/testsuite/ld-riscv-elf/c-lui-2.d
@@ -1,7 +1,7 @@
#name: c.lui to c.li relaxation
#source: c-lui-2.s
#as: -march=rv32ic
-#ld: -melf32lriscv -Tc-lui-2.ld
+#ld: -m[riscv_choose_ilp32_emul] -Tc-lui-2.ld
#objdump: -d -M no-aliases,numeric
.*: file format .*
diff --git a/ld/testsuite/ld-riscv-elf/c-lui.d b/ld/testsuite/ld-riscv-elf/c-lui.d
index 382eca88dc..f1cf0b42c3 100644
--- a/ld/testsuite/ld-riscv-elf/c-lui.d
+++ b/ld/testsuite/ld-riscv-elf/c-lui.d
@@ -1,7 +1,7 @@
#name: lui to c.lui relaxation
#source: c-lui.s
#as: -march=rv32ic
-#ld: -melf32lriscv
+#ld: -m[riscv_choose_ilp32_emul]
#objdump: -d -M no-aliases,numeric
.*: file format .*
diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
index 597ff67535..c6022bec26 100644
--- a/ld/testsuite/ld-riscv-elf/call-relax.d
+++ b/ld/testsuite/ld-riscv-elf/call-relax.d
@@ -4,6 +4,6 @@
#source: call-relax-2.s
#source: call-relax-3.s
#as: -march=rv32ic -mno-arch-attr
-#ld: -melf32lriscv
+#ld: -m[riscv_choose_ilp32_emul]
#objdump: -d
#pass
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 86910e60ec..cb7c2ab9fb 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -19,6 +19,24 @@
# MA 02110-1301, USA.
#
+proc riscv_choose_ilp32_emul {} {
+ if { [istarget "riscvbe-*"] \
+ || [istarget "riscv32be-*"] \
+ || [istarget "riscv64be-*"] } {
+ return "elf32briscv"
+ }
+ return "elf32lriscv"
+}
+
+proc riscv_choose_lp64_emul {} {
+ if { [istarget "riscvbe-*"] \
+ || [istarget "riscv32be-*"] \
+ || [istarget "riscv64be-*"] } {
+ return "elf64briscv"
+ }
+ return "elf64lriscv"
+}
+
# target: rv32 or rv64.
# output: Which output you want? (exe, pie, .so)
proc run_dump_test_ifunc { name target output} {
@@ -42,11 +60,11 @@ proc run_dump_test_ifunc { name target output} {
switch -- $target {
rv32 {
set asflags "$asflags -march=rv32i -mabi=ilp32"
- set ldflags "$ldflags -melf32lriscv"
+ set ldflags "$ldflags -m[riscv_choose_ilp32_emul]"
}
rv64 {
set asflags "$asflags -march=rv64i -mabi=lp64 -defsym __64_bit__=1"
- set ldflags "$ldflags -melf64lriscv"
+ set ldflags "$ldflags -m[riscv_choose_lp64_emul]"
}
}
@@ -89,21 +107,20 @@ if [istarget "riscv*-*-*"] {
run_dump_test "attr-merge-priv-spec-failed-04"
run_dump_test "attr-merge-priv-spec-failed-05"
run_dump_test "attr-merge-priv-spec-failed-06"
- run_ld_link_tests {
- { "Weak reference 32" "-T weakref.ld -melf32lriscv" ""
- "-march=rv32i -mabi=ilp32" {weakref32.s}
- {{objdump -d weakref32.d}} "weakref32"}
- { "Weak reference 64" "-T weakref.ld -melf64lriscv" ""
- "-march=rv64i -mabi=lp64" {weakref64.s}
- {{objdump -d weakref64.d}} "weakref64"}
- }
+ run_ld_link_tests [list \
+ [list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
+ "-march=rv32i -mabi=ilp32" {weakref32.s} \
+ {{objdump -d weakref32.d}} "weakref32"] \
+ [list "Weak reference 64" "-T weakref.ld -m[riscv_choose_lp64_emul]" "" \
+ "-march=rv64i -mabi=lp64" {weakref64.s} \
+ {{objdump -d weakref64.d}} "weakref64"]]
# The following tests require shared library support.
if ![check_shared_lib_support] {
return
}
- set abis { rv32gc ilp32 elf32lriscv rv64gc lp64 elf64lriscv }
+ set abis { rv32gc ilp32 [riscv_choose_ilp32_emul] rv64gc lp64 [riscv_choose_lp64_emul] }
foreach { arch abi emul } $abis {
# This checks whether our linker scripts handle __global_pointer$
# correctly. It should be defined in executables and PIE, but not
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d
index 039de102c3..895c6cc581 100644
--- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d
+++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d
@@ -1,5 +1,5 @@
#name: %pcrel_lo overflow with an addend
#source: pcrel-lo-addend-2.s
#as: -march=rv32ic
-#ld: -melf32lriscv --no-relax
+#ld: -m[riscv_choose_ilp32_emul] --no-relax
#error: .*dangerous relocation: %pcrel_lo overflow with an addend
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
index ad658be844..92d41528a4 100644
--- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
+++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
@@ -1,5 +1,5 @@
#name: %pcrel_lo section symbol with an addend
#source: pcrel-lo-addend.s
#as: -march=rv32ic
-#ld: -melf32lriscv
+#ld: -m[riscv_choose_ilp32_emul]
#error: .*dangerous relocation: %pcrel_lo section symbol with an addend
diff --git a/ld/testsuite/ld-riscv-elf/weakref32.d b/ld/testsuite/ld-riscv-elf/weakref32.d
index eaeb6dae7e..279481d223 100644
--- a/ld/testsuite/ld-riscv-elf/weakref32.d
+++ b/ld/testsuite/ld-riscv-elf/weakref32.d
@@ -1,5 +1,5 @@
-.*: file format elf32-littleriscv
+.*: file format elf32-(little|big)riscv
Disassembly of section \.text:
diff --git a/ld/testsuite/ld-riscv-elf/weakref64.d b/ld/testsuite/ld-riscv-elf/weakref64.d
index cc718a91a3..c8f4c10339 100644
--- a/ld/testsuite/ld-riscv-elf/weakref64.d
+++ b/ld/testsuite/ld-riscv-elf/weakref64.d
@@ -1,5 +1,5 @@
-.*: file format elf64-littleriscv
+.*: file format elf64-(little|big)riscv
Disassembly of section \.text:
diff --git a/ld/testsuite/ld-scripts/empty-address-2a.d b/ld/testsuite/ld-scripts/empty-address-2a.d
index 3b5a2d68f7..2619c48fc1 100644
--- a/ld/testsuite/ld-scripts/empty-address-2a.d
+++ b/ld/testsuite/ld-scripts/empty-address-2a.d
@@ -1,7 +1,7 @@
#source: empty-address-2.s
#ld: -Ttext 0x0000000 -Tdata 0x200 -T empty-address-2a.t
#nm: -n
-#xfail: frv-*-*linux* riscv64-*-* tic54x-*-*
+#xfail: frv-*-*linux* riscv64-*-* riscv64be-*-* tic54x-*-*
#...
0+0 T _start
#...
diff --git a/ld/testsuite/ld-scripts/empty-address-2b.d b/ld/testsuite/ld-scripts/empty-address-2b.d
index 3b530c94d8..ebe8461bb3 100644
--- a/ld/testsuite/ld-scripts/empty-address-2b.d
+++ b/ld/testsuite/ld-scripts/empty-address-2b.d
@@ -1,7 +1,7 @@
#source: empty-address-2.s
#ld: -Ttext 0x0000000 -Tdata 0x200 -T empty-address-2b.t
#nm: -n
-#xfail: frv-*-*linux* riscv64-*-* tic54x-*-*
+#xfail: frv-*-*linux* riscv64-*-* riscv64be-*-* tic54x-*-*
#...
0+0 T _start
#...
--
2.26.2
More information about the Binutils
mailing list