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[PATCH][GAS][AArch64] Fix MSR/MRS Encoding and Decoding
- From: Tamar Christina <tamar dot christina at arm dot com>
- To: binutils at sourceware dot org
- Cc: nd at arm dot com, Richard dot Earnshaw at arm dot com, marcus dot shawcroft at arm dot com
- Date: Thu, 8 Mar 2018 18:14:01 +0000
- Subject: [PATCH][GAS][AArch64] Fix MSR/MRS Encoding and Decoding
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- Authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tamar dot Christina at arm dot com;
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Hi All,
This patch corrects the opcode and mask for the MSR and MRS instructions.
These two instructions have bit 20 set but the current CORE_INSN do not
correctly have bit 20 set causing invalid encoding and decoding.
Cross compiled and regtested:
* aarch64-none-elf
* aarch64_be-none-elf
and no regressions.
Bootstrapped and regtested on:
* aarch64-none-elf
* aarch64-none-elf (32 bit schroot)
and no regressions.
Ok for master?
Thanks,
Tamar
opcodes/
2018-03-08 Tamar Christina <tamar.christina@arm.com>
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Fix MSR and MRS encoding.
gas/
2018-03-08 Tamar Christina <tamar.christina@arm.com>
* testsuite/gas/aarch64/sysreg-1.d: Update encodings.
--
diff --git a/gas/testsuite/gas/aarch64/sysreg-1.d b/gas/testsuite/gas/aarch64/sysreg-1.d
index fb9991d1116307c072063bb0830d8f04d7410aec..ee604bf101619af45e8d0c3a5c7de75ffa219f08 100644
--- a/gas/testsuite/gas/aarch64/sysreg-1.d
+++ b/gas/testsuite/gas/aarch64/sysreg-1.d
@@ -4283,13 +4283,13 @@ Disassembly of section \.text:
42cc: d53c400f mrs x15, spsr_el2
42d0: d51e400f msr spsr_el3, x15
42d4: d53e400f mrs x15, spsr_el3
- 42d8: d500000f msr s0_0_c0_c0_0, x15
- 42dc: d520000f mrs x15, s0_0_c0_c0_0
- 42e0: d50ffffb sys #7, C15, C15, #7, x27
- 42e4: d52ffffb sysl x27, #7, C15, C15, #7
+ 42d8: d510000f msr s2_0_c0_c0_0, x15
+ 42dc: d530000f mrs x15, s2_0_c0_c0_0
+ 42e0: d51ffffb msr s3_7_c15_c15_7, x27
+ 42e4: d53ffffb mrs x27, s3_7_c15_c15_7
42e8: d514680e msr s2_4_c6_c8_0, x14
42ec: d534680e mrs x14, s2_4_c6_c8_0
- 42f0: d50ae444 sys #2, C14, C4, #2, x4
- 42f4: d52ae444 sysl x4, #2, C14, C4, #2
- 42f8: d501d167 msr s0_1_c13_c1_3, x7
- 42fc: d521d167 mrs x7, s0_1_c13_c1_3
+ 42f0: d51ae444 msr s3_2_c14_c4_2, x4
+ 42f4: d53ae444 mrs x4, s3_2_c14_c4_2
+ 42f8: d511d167 msr s2_1_c13_c1_3, x7
+ 42fc: d531d167 mrs x7, s2_1_c13_c1_3
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index af36a15ab013c4f1aed53a9cb44d6435ffd22c34..ce0178690343c526d5a90182ac8a1318aac1869f 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -12016,63 +12016,151 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 21) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 25) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1010101xx0xxxxxxxxxxxxxxxxxxxxx
- msr. */
- return 1157;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10101x1xxx00xxxxx00xxxxxxxxxxxx
+ msr. */
+ return 1157;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10101x1xxx00xxxxx10xxxxxxxxxxxx
+ hint. */
+ return 1158;
+ }
+ }
+ else
+ {
+ if (((word >> 5) & 0x1) == 0)
+ {
+ if (((word >> 6) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10101x1xxx00xxxxxx1xxxxx00xxxxx
+ dsb. */
+ return 1174;
+ }
+ else
+ {
+ if (((word >> 7) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10101x1xxx00xxxxxx1xxxx010xxxxx
+ clrex. */
+ return 1173;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10101x1xxx00xxxxxx1xxxx110xxxxx
+ isb. */
+ return 1176;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10101x1xxx00xxxxxx1xxxxxx1xxxxx
+ dmb. */
+ return 1175;
+ }
+ }
}
else
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 21) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1010111xx0xxxxxxxxxx0xxxxxxxxxx
- braa. */
- return 637;
+ x10101x1xx001xxxxxxxxxxxxxxxxxxx
+ sys. */
+ return 1177;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1010111xx0xxxxxxxxxx1xxxxxxxxxx
- brab. */
- return 638;
+ x10101x1xx101xxxxxxxxxxxxxxxxxxx
+ sysl. */
+ return 1183;
}
}
}
else
{
- if (((word >> 25) & 0x1) == 0)
+ if (((word >> 21) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1010101xx1xxxxxxxxxxxxxxxxxxxxx
- sysl. */
- return 1183;
+ if (((word >> 25) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010101xx01xxxxxxxxxxxxxxxxxxxx
+ msr. */
+ return 1182;
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010111xx01xxxxxxxxx0xxxxxxxxxx
+ braa. */
+ return 637;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010111xx01xxxxxxxxx1xxxxxxxxxx
+ brab. */
+ return 638;
+ }
+ }
}
else
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 25) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1010111xx1xxxxxxxxxx0xxxxxxxxxx
- blraa. */
- return 639;
+ x1010101xx11xxxxxxxxxxxxxxxxxxxx
+ mrs. */
+ return 1184;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1010111xx1xxxxxxxxxx1xxxxxxxxxx
- blrab. */
- return 640;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010111xx11xxxxxxxxx0xxxxxxxxxx
+ blraa. */
+ return 639;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010111xx11xxxxxxxxx1xxxxxxxxxx
+ blrab. */
+ return 640;
+ }
}
}
}
@@ -19130,17 +19218,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
case 940: return NULL; /* stllrh --> NULL. */
case 942: value = 946; break; /* ldnp --> ldp. */
case 946: return NULL; /* ldp --> NULL. */
- case 1157: value = 1158; break; /* msr --> hint. */
- case 1158: value = 1173; break; /* hint --> clrex. */
- case 1173: value = 1174; break; /* clrex --> dsb. */
- case 1174: value = 1175; break; /* dsb --> dmb. */
- case 1175: value = 1176; break; /* dmb --> isb. */
- case 1176: value = 1177; break; /* isb --> sys. */
- case 1177: value = 1182; break; /* sys --> msr. */
- case 1182: value = 2024; break; /* msr --> cfinv. */
+ case 1157: value = 2024; break; /* msr --> cfinv. */
case 2024: return NULL; /* cfinv --> NULL. */
- case 1183: value = 1184; break; /* sysl --> mrs. */
- case 1184: return NULL; /* mrs --> NULL. */
case 434: value = 435; break; /* st4 --> st1. */
case 435: value = 436; break; /* st1 --> st2. */
case 436: value = 437; break; /* st2 --> st3. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 12b980e9f5455e43a6db0f160f272ece9c494218..002db603109e6f44f118bcc7bad3b57ea7a2cd38 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3477,9 +3477,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),
CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
- CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, 0),
+ CORE_INSN ("msr", 0xd5100000, 0xfff00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, 0),
CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
- CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, 0),
+ CORE_INSN ("mrs", 0xd5300000, 0xfff00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, 0),
V8_3_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
V8_3_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),