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[committed] MIPS16/opcodes: Free up `M' operand code


The `M' and `m' MIPS16 operand codes are functionally the same, denoting 
a 7-bit register list that is encoded the same way for both SAVE and 
RESTORE.  Use `m' for both instructions then, making `M' available for a 
different use.

	opcodes/
	* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
	(mips16_opcodes): Replace `M' with `m' for "restore".

	include/
	* opcode/mips.h: Remove `M' operand code.
---
binutils-mips16-save-restore-op.diff
Index: binutils/include/opcode/mips.h
===================================================================
--- binutils.orig/include/opcode/mips.h	2017-06-30 02:46:43.961977099 +0100
+++ binutils/include/opcode/mips.h	2017-06-30 02:46:48.317456837 +0100
@@ -1889,13 +1889,12 @@ extern int bfd_mips_num_opcodes;
    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
-   "m" 7 bit register list for save instruction (18 bit extended)
-   "M" 7 bit register list for restore instruction (18 bit extended)
+   "m" 7 bit register list for SAVE/RESTORE instruction (18 bit extended)
 
    Characters used so far, for quick reference when adding more:
    "0123456 89"
    ".[]<>"
-   "ABCDEFGHI KLMNOPQRSTUVWXYZ"
+   "ABCDEFGHI KL NOPQRSTUVWXYZ"
    "abcde   ijklmnopqrs uvwxyz"
   */
 
Index: binutils/opcodes/mips16-opc.c
===================================================================
--- binutils.orig/opcodes/mips16-opc.c	2017-06-30 01:39:14.272751908 +0100
+++ binutils/opcodes/mips16-opc.c	2017-06-30 02:46:48.345901680 +0100
@@ -62,7 +62,6 @@ decode_mips16_operand (char type, bfd_bo
 
     case 'G': SPECIAL (0, 0, REG28);
     case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
-    case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST);
     case 'N': REG (5, 0, COPRO);
     case 'O': UINT (3, 21);
     case 'Q': REG (5, 16, HW);
@@ -445,7 +444,7 @@ const struct mips_opcode mips16_opcodes[
 {"xor",	    "x,y",	0xe80e, 0xf81f,		MOD_1|RD_2,		SH,		I1,	0,	0 },
 {"xori",    "x,u",	0xf0006880, 0xf800f8e0,	WR_1,			0,		0,	E2,	0 },
   /* MIPS16e additions; see above for compact jumps.  */
-{"restore", "M",	0x6400, 0xff80,		WR_31|NODS,		MOD_SP,		I32,	0,	0 },
+{"restore", "m",	0x6400, 0xff80,		WR_31|NODS,		MOD_SP,		I32,	0,	0 },
 {"save",    "m",	0x6480, 0xff80,		NODS,			RD_31|MOD_SP,	I32,	0,	0 },
 {"sdbbp",   "",		0xe801, 0xffff,		TRAP,			SH,		I32,	0,	0 },
 {"sdbbp",   "6",	0xe801, 0xf81f,		TRAP,			SH,		I32,	0,	0 },


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