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[PATCH 5/4] x86: helper changes to i386-gen.c

From: "Jan Beulich" <JBeulich at suse dot com>
To: <binutils at sourceware dot org>
Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
Date: Mon, 18 Dec 2017 01:03:46 -0700
Subject: [PATCH 5/4] x86: helper changes to i386-gen.c
Authentication-results: sourceware.org; auth=none
References: <5A33A9D802000078001979BE@prv-mh.provo.novell.com>

I've just realized that I forgot to send the helper patch I've been
using, presumably just for reference (as mentioned in the overview
mail, I could certainly transform this into a properly shaped,
committable patch). Note that the opcode table adjustments are
to avoid false positives; the entries changed ae bogus anyway,
but that'll be the subject of my default-operand-size series which
will still take some time until it is ready for posting.

Jan

--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -1082,7 +1082,11 @@ process_i386_operand_type (FILE *table,
 
   if (strcmp (op, "0"))
     {
-      int baseindex = 0;
+      int baseindex = 0, disp = 0;
+      int reg = 0, reg8 = 0, reg16 = 0, reg32 = 0, reg64 = 0;
+      int simd = 0, regxmm = 0, regymm = 0, regzmm = 0;
+      int byte = 0, word = 0, dword = 0, qword = 0, anysize = 0;
+      int xmmword = 0, ymmword = 0, zmmword = 0;
 
       last = op + strlen (op);
       for (next = op; next && next < last; )
@@ -1093,6 +1097,38 @@ process_i386_operand_type (FILE *table,
 	      set_bitfield (str, types, 1, ARRAY_SIZE (types), lineno);
 	      if (strcasecmp(str, "BaseIndex") == 0)
 		baseindex = 1;
+	      else if (strncasecmp(str, "Disp", 4) == 0)
+		disp = 1;
+	      else if (strcasecmp(str, "Reg8") == 0)
+		reg8 = reg = 1;
+	      else if (strcasecmp(str, "Reg16") == 0)
+		reg16 = reg = 1;
+	      else if (strcasecmp(str, "Reg32") == 0)
+		reg32 = reg = 1;
+	      else if (strcasecmp(str, "Reg64") == 0)
+		reg64 = reg = 1;
+	      else if (strcasecmp(str, "RegXMM") == 0)
+		regxmm = simd = 1;
+	      else if (strcasecmp(str, "RegYMM") == 0)
+		regymm = simd = 1;
+	      else if (strcasecmp(str, "RegZMM") == 0)
+		regzmm = simd = 1;
+	      else if (strcasecmp(str, "Byte") == 0)
+		byte = 1;
+	      else if (strcasecmp(str, "Word") == 0)
+		word = 1;
+	      else if (strcasecmp(str, "Dword") == 0)
+		dword = 1;
+	      else if (strcasecmp(str, "Qword") == 0)
+		qword = 1;
+	      else if (strcasecmp(str, "Xmmword") == 0)
+		xmmword = 1;
+	      else if (strcasecmp(str, "Ymmword") == 0)
+		ymmword = 1;
+	      else if (strcasecmp(str, "Zmmword") == 0)
+		zmmword = 1;
+	      else if (strcasecmp(str, "Anysize") == 0)
+		anysize = 1;
 	    }
 	}
 
@@ -1106,6 +1142,38 @@ process_i386_operand_type (FILE *table,
 	  if (!active_cpu_flags.bitfield.cpuno64)
 	    set_bitfield("Disp32S", types, 1, ARRAY_SIZE (types), lineno);
 	}
+
+      if (stage == stage_opcodes && (baseindex || disp))
+	{
+	  if (reg8 && !byte && !anysize)
+	    fprintf (stderr, "%s:%d: Reg8 but no Byte mem\n", filename, lineno);
+	  if (reg16 && !word && !anysize)
+	    fprintf (stderr, "%s:%d: Reg16 but no Word mem\n", filename, lineno);
+	  if (reg32 && !dword && !anysize)
+	    fprintf (stderr, "%s:%d: Reg32 but no Dword mem\n", filename, lineno);
+	  if (reg64 && !qword && !anysize)
+	    fprintf (stderr, "%s:%d: Reg64 but no Qword mem\n", filename, lineno);
+	  if (regxmm && !xmmword && !anysize && (ymmword || zmmword))
+	    fprintf (stderr, "%s:%d: RegXMM but no Xmmword mem\n", filename, lineno);
+	  if (regymm && !ymmword && !anysize && (xmmword || zmmword))
+	    fprintf (stderr, "%s:%d: RegYMM but no Ymmword mem\n", filename, lineno);
+	  if (regzmm && !zmmword && !anysize && (xmmword || ymmword))
+	    fprintf (stderr, "%s:%d: RegZMM but no Zmmword mem\n", filename, lineno);
+	}
+      if (!reg8 && byte && reg)
+	fprintf (stderr, "%s:%d: Byte and RegN but no Reg8\n", filename, lineno);
+      if (!reg16 && word && reg)
+	fprintf (stderr, "%s:%d: Word and RegN but no Reg16\n", filename, lineno);
+      if (!reg32 && dword && reg)
+	fprintf (stderr, "%s:%d: Dword and RegN but no Reg32\n", filename, lineno);
+      if (!reg64 && qword && reg)
+	fprintf (stderr, "%s:%d: Qword and RegN but no Reg64\n", filename, lineno);
+      if (!regxmm && xmmword && simd)
+	fprintf (stderr, "%s:%d: Xmmword and Reg?MM but no RegXMM\n", filename, lineno);
+      if (!regymm && ymmword && simd)
+	fprintf (stderr, "%s:%d: Ymmword and Reg?MM but no RegYMM\n", filename, lineno);
+      if (!regzmm && zmmword && simd)
+	fprintf (stderr, "%s:%d: Zmmword and Reg?MM but no RegZMM\n", filename, lineno);
     }
   output_operand_type (table, types, ARRAY_SIZE (types), stage,
 		       indent);
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -66,9 +66,9 @@ movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|
 movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex, Reg64 }
 movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 }
 // Intel Syntax next 3 insns
-movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 }
-movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|ATTSyntax, { Reg32|Unspecified|BaseIndex, Reg64 }
+movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg|Word|Unspecified|BaseIndex, Reg32|Reg64 }
+movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|ATTSyntax, { Reg|Dword|Unspecified|BaseIndex, Reg64 }
 movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 }
 movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 }
 movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex, Reg64 }
@@ -79,8 +79,8 @@ movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|
 movzw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 }
 // Intel Syntax next 2 insns (the 64-bit variants are not particulary
 // useful since the zero extend 32->64 is implicit, but we can encode them).
-movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 }
+movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg|Word|Unspecified|BaseIndex, Reg32|Reg64 }
 movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 }
 movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 }

Follow-Ups:
- Re: [PATCH 5/4] x86: helper changes to i386-gen.c
  - From: H.J. Lu

References:
- [PATCH 0/4] x86: operand handling consolidation
  - From: Jan Beulich

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