[PATCH 2/4] x86: drop FloatReg and FloatAcc

["Jan Beulich" <JBeulich at suse dot com>]

Express them as Reg|Tbyte and Acc|Tbyte respectively.

gas/
2017-12-15  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (operand_type_check): Extend comment.
	(match_reg_size): Also check .tbyte.
	(match_mem_size): No longer check .tbyte here.
	(md_assemble): Drop .floatacc check.
	(check_byte_reg): Drop .floatreg and .floatacc checks.
	(process_operands, parse_real_register): Replace .floatreg
	check.

opcodes/
2017-12-15  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (operand_type_shorthands): Add FloatAcc and
	FloatReg.
	(operand_types): Drop FloatAcc and FloatReg.
	* i386-opc.h (enum of operand types): Likewise. Extend comment.
	(union i386_operand_type): Drop floatacc and floatreg.
	* i386-reg.tbl (st, st(0)): Replace FloatAcc by Acc.
	* i386-init.h, i386-tbl.h: Re-generate.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1807,7 +1807,7 @@ operand_type_check (i386_operand_type t,
   return 0;
 }
 
-/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
+/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
    operand J for instruction template T.  */
 
 static INLINE int
@@ -1820,7 +1820,9 @@ match_reg_size (const insn_template *t,
 	   || (i.types[j].bitfield.dword
 	       && !t->operand_types[j].bitfield.dword)
 	   || (i.types[j].bitfield.qword
-	       && !t->operand_types[j].bitfield.qword));
+	       && !t->operand_types[j].bitfield.qword)
+	   || (i.types[j].bitfield.tbyte
+	       && !t->operand_types[j].bitfield.tbyte));
 }
 
 /* Return 1 if there is no conflict in any size on operand J for
@@ -1835,8 +1837,6 @@ match_mem_size (const insn_template *t,
 		&& !t->operand_types[j].bitfield.unspecified)
 	       || (i.types[j].bitfield.fword
 		   && !t->operand_types[j].bitfield.fword)
-	       || (i.types[j].bitfield.tbyte
-		   && !t->operand_types[j].bitfield.tbyte)
 	       || (i.types[j].bitfield.xmmword
 		   && !t->operand_types[j].bitfield.xmmword)
 	       || (i.types[j].bitfield.ymmword
@@ -3768,8 +3768,7 @@ md_assemble (char *line)
     for (j = 0; j < i.operands; j++)
       if (i.types[j].bitfield.inoutportreg
 	  || i.types[j].bitfield.shiftcount
-	  || i.types[j].bitfield.acc
-	  || i.types[j].bitfield.floatacc)
+	  || i.types[j].bitfield.acc)
 	i.reg_operands--;
 
   /* ImmExt should be processed after SSE2AVX.  */
@@ -5661,9 +5660,7 @@ check_byte_reg (void)
 	  || i.types[op].bitfield.sreg3
 	  || i.types[op].bitfield.control
 	  || i.types[op].bitfield.debug
-	  || i.types[op].bitfield.test
-	  || i.types[op].bitfield.floatreg
-	  || i.types[op].bitfield.floatacc)
+	  || i.types[op].bitfield.test)
 	{
 	  as_bad (_("`%s%s' not allowed with `%s%c'"),
 		  register_prefix,
@@ -6122,7 +6119,7 @@ duplicate:
 	     0 or 1.  */
 	  unsigned int op;
 
-	  if (i.types[0].bitfield.floatreg
+	  if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
 	      || operand_type_check (i.types[0], reg))
 	    op = 0;
 	  else
@@ -9768,7 +9765,7 @@ parse_real_register (char *reg_string, c
       && !cpu_arch_flags.bitfield.cpui386)
     return (const reg_entry *) NULL;
 
-  if (r->reg_type.bitfield.floatreg
+  if (r->reg_type.bitfield.tbyte
       && !cpu_arch_flags.bitfield.cpu8087
       && !cpu_arch_flags.bitfield.cpu287
       && !cpu_arch_flags.bitfield.cpu387)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -341,6 +341,8 @@ static const initializer operand_type_sh
   { "Reg16",    "Reg|Word" },
   { "Reg32",    "Reg|Dword" },
   { "Reg64",    "Reg|Qword" },
+  { "FloatAcc", "Acc|Tbyte" },
+  { "FloatReg", "Reg|Tbyte" },
 };
 
 static initializer operand_type_init[] =
@@ -640,7 +642,6 @@ static bitfield opcode_modifiers[] =
 static bitfield operand_types[] =
 {
   BITFIELD (Reg),
-  BITFIELD (FloatReg),
   BITFIELD (RegMMX),
   BITFIELD (RegXMM),
   BITFIELD (RegYMM),
@@ -667,7 +668,6 @@ static bitfield operand_types[] =
   BITFIELD (SReg2),
   BITFIELD (SReg3),
   BITFIELD (Acc),
-  BITFIELD (FloatAcc),
   BITFIELD (JumpAbsolute),
   BITFIELD (EsSeg),
   BITFIELD (RegMem),
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -687,8 +687,6 @@ enum
 {
   /* Register (qualified by Byte, Word, etc) */
   Reg = 0,
-  /* Floating pointer stack register */
-  FloatReg,
   /* MMX register */
   RegMMX,
   /* SSE register */
@@ -740,10 +738,8 @@ enum
   Disp32S,
   /* 64 bit displacement */
   Disp64,
-  /* Accumulator %al/%ax/%eax/%rax */
+  /* Accumulator %al/%ax/%eax/%rax/%st(0) */
   Acc,
-  /* Floating pointer top stack register %st(0) */
-  FloatAcc,
   /* Register which can be used for base or index in memory operand.  */
   BaseIndex,
   /* Register to hold in/out port addr = dx */
@@ -809,7 +805,6 @@ typedef union i386_operand_type
   struct
     {
       unsigned int reg:1;
-      unsigned int floatreg:1;
       unsigned int regmmx:1;
       unsigned int regxmm:1;
       unsigned int regymm:1;
@@ -833,7 +828,6 @@ typedef union i386_operand_type
       unsigned int disp32s:1;
       unsigned int disp64:1;
       unsigned int acc:1;
-      unsigned int floatacc:1;
       unsigned int baseindex:1;
       unsigned int inoutportreg:1;
       unsigned int shiftcount:1;
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -19,7 +19,7 @@
 // 02110-1301, USA.
 
 // Make %st first as we test for it.
-st, FloatReg|FloatAcc, 0, 0, 11, 33
+st, FloatReg|Acc, 0, 0, 11, 33
 // 8 bit regs
 al, Reg8|Acc, 0, 0, Dw2Inval, Dw2Inval
 cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
@@ -292,7 +292,7 @@ eip, BaseIndex, RegRex64, RegEip, 8, Dw2
 riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
 eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
 // fp regs.
-st(0), FloatReg|FloatAcc, 0, 0, 11, 33
+st(0), FloatReg|Acc, 0, 0, 11, 33
 st(1), FloatReg, 0, 1, 12, 34
 st(2), FloatReg, 0, 2, 13, 35
 st(3), FloatReg, 0, 3, 14, 36