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RE: [PATCH][MIPS] Add Global INValidate instructions
- From: Faraz Shahbazker <Faraz dot Shahbazker at mips dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>, Maciej Rozycki <Maciej dot Rozycki at mips dot com>
- Cc: Matthew Fortune <Matthew dot Fortune at mips dot com>
- Date: Wed, 29 Nov 2017 19:16:54 +0000
- Subject: RE: [PATCH][MIPS] Add Global INValidate instructions
- Authentication-results: sourceware.org; auth=none
- References: <1d3f8dba-f97e-5471-a2c0-8d9282e87724@mips.com>
Resubmitting with correct format.
Hi,
The following patch adds support for the Global INValidate (GINV)
instructions in Release 6 of the MIPS Architecture. The changes are:
* New instruction GINVI, GINVT: enabled by option `-mginv'.
* New instruction GINVGT: enabled by `-mginv -mvirt'.
* Bit-17 in MIPS.abiflags is set when GINV extension is enabled.
The new ginv* instructions are described in Section 3.2 of the MIPS
Instruction Set v6.06
(https://www.mips.com/?do-download=the-mips32-instruction-set-v6-06)
This patch cannot be committed yet, since copyright assignment to FSF
from the new MIPS entity is still pending. Please review and approve
for a future commit.
Regards,
Faraz Shahbazker
ChangeLog:
bfd/
* elfxx-mips.c (print_mips_ases): Add GINV extension.
binutils/
* readelf.c (print_mips_ases) Add GINV extension.
gas/
* config/tc-mips.c (options) <OPTION_GINV, OPTION_NOGINV>:
New.
(md_longopts): Add -m[no-]ginv options.
(mips_ases): Likewise.
(mips_set_ase): Handle combination of VX and GINV extensions.
(mips_convert_ase_flags): Add GINV extension.
(md_show_usage): Add -m[no-]ginv options.
* doc/as.texinfo: Add description for -m[no-]ginv.
* doc/c-mips.texi: Likewise.
include/
* elf/mips.h (AFL_ASE_GINV): New.
(AFL_ASE_MASK): Update mask for all ASEs.
* opcode/mips.h: Add comments for new operand format "+\".
(ASE_GINV): New.
(ASE_GINV_VIRT): Likewise.
opcodes/
* mips-opc.c (decode_mips_operand) <+\>: New case.
(GINV): New.
(GINVVZ): Likewise.
(mips_opcodes): Add instructions GINVI, GINVT, GINVGT.
* micromips-opc.c (decode_micromips_operand) <+\>: New case.
(GINV): New.
(GINVVZ): Likewise.
(micromips_opcodes): Add instructions GINVI, GINVT, GINVGT.
* mips-dis.c (mips_arch_choices): Add GINV and VIRT_GINV ASEs
to mips32r6 and mips64r6 descriptors.
(mips_calculate_combination_ases): Set VIRT_GINV
appropriately.
(parse_mips_ase_option): Handle -mginv option.
gas/testsuite/
* gas/mips/mips.exp: Add new tests.
* gas/mips/ase-errors-1.s: Add new test cases.
* gas/mips/ase-errors-2.s: Likewise.
* gas/mips/ginv.s: New file.
* gas/mips/ginv-error.s: Likewise.
* gas/mips/ginv-virt-error.s: Likewise.
* gas/mips/ginv.d: Likewise.
* gas/mips/ginv-dis.d: Likewise.
* gas/mips/ginv-virt.d: Likewise.
* gas/mips/ginv-virt-dis.d: Likewise.
* gas/mips/micromipsr@ginv.d: Likewise.
* gas/mips/micromipsr@ginv-dis.d: Likewise.
* gas/mips/micromipsr@ginv-virt.d: Likewise.
* gas/mips/micromipsr@ginv-virt-dis.d: Likewise.
* gas/mips/ase-errors-1.l: Update reference output.
* gas/mips/ase-errors-2.l: Likewise.
* gas/mips/ginv-error.l: New file.
* gas/mips/ginv-virt-error.l: New file.
---
bfd/elfxx-mips.c | 2 ++
binutils/readelf.c | 2 ++
gas/config/tc-mips.c | 25 +++++++++++++++++++++++-
gas/doc/as.texinfo | 7 +++++++
gas/doc/c-mips.texi | 6 ++++++
gas/testsuite/gas/mips/ase-errors-1.l | 6 ++++++
gas/testsuite/gas/mips/ase-errors-1.s | 13 ++++++++++++
gas/testsuite/gas/mips/ase-errors-2.l | 6 ++++++
gas/testsuite/gas/mips/ase-errors-2.s | 13 ++++++++++++
gas/testsuite/gas/mips/ginv-dis.d | 15 ++++++++++++++
gas/testsuite/gas/mips/ginv-error.l | 2 ++
gas/testsuite/gas/mips/ginv-error.s | 8 ++++++++
gas/testsuite/gas/mips/ginv-virt-dis.d | 17 ++++++++++++++++
gas/testsuite/gas/mips/ginv-virt-error.l | 3 +++
gas/testsuite/gas/mips/ginv-virt-error.s | 10 ++++++++++
gas/testsuite/gas/mips/ginv-virt.d | 17 ++++++++++++++++
gas/testsuite/gas/mips/ginv.d | 14 +++++++++++++
gas/testsuite/gas/mips/ginv.s | 13 ++++++++++++
gas/testsuite/gas/mips/micromips@ginv-dis.d | 16 +++++++++++++++
gas/testsuite/gas/mips/micromips@ginv-virt-dis.d | 17 ++++++++++++++++
gas/testsuite/gas/mips/micromips@ginv-virt.d | 17 ++++++++++++++++
gas/testsuite/gas/mips/micromips@ginv.d | 16 +++++++++++++++
gas/testsuite/gas/mips/mips.exp | 8 ++++++++
include/elf/mips.h | 3 ++-
include/opcode/mips.h | 11 +++++++++++
opcodes/micromips-opc.c | 11 +++++++++++
opcodes/mips-dis.c | 12 ++++++++++--
opcodes/mips-opc.c | 9 +++++++++
28 files changed, 295 insertions(+), 4 deletions(-)
create mode 100644 gas/testsuite/gas/mips/ginv-dis.d
create mode 100644 gas/testsuite/gas/mips/ginv-error.l
create mode 100644 gas/testsuite/gas/mips/ginv-error.s
create mode 100644 gas/testsuite/gas/mips/ginv-virt-dis.d
create mode 100644 gas/testsuite/gas/mips/ginv-virt-error.l
create mode 100644 gas/testsuite/gas/mips/ginv-virt-error.s
create mode 100644 gas/testsuite/gas/mips/ginv-virt.d
create mode 100644 gas/testsuite/gas/mips/ginv.d
create mode 100644 gas/testsuite/gas/mips/ginv.s
create mode 100644 gas/testsuite/gas/mips/micromips@ginv-dis.d
create mode 100644 gas/testsuite/gas/mips/micromips@ginv-virt-dis.d
create mode 100644 gas/testsuite/gas/mips/micromips@ginv-virt.d
create mode 100644 gas/testsuite/gas/mips/micromips@ginv.d
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 8745e60..15fd6bb 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -15609,6 +15609,8 @@ print_mips_ases (FILE *file, unsigned int mask)
fputs ("\n\tXPA ASE", file);
if (mask & AFL_ASE_MIPS16E2)
fputs ("\n\tMIPS16e2 ASE", file);
+ if (mask & AFL_ASE_GINV)
+ fputs ("\n\tGINV ASE", file);
if (mask == 0)
fprintf (file, "\n\t%s", _("None"));
else if ((mask & ~AFL_ASE_MASK) != 0)
diff --git a/binutils/readelf.c b/binutils/readelf.c
index a1f43e6..7729501 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -15412,6 +15412,8 @@ print_mips_ases (unsigned int mask)
fputs ("\n\tXPA ASE", stdout);
if (mask & AFL_ASE_MIPS16E2)
fputs ("\n\tMIPS16e2 ASE", stdout);
+ if (mask & AFL_ASE_GINV)
+ fputs ("\n\tGINV ASE", stdout);
if (mask == 0)
fprintf (stdout, "\n\t%s", _("None"));
else if ((mask & ~AFL_ASE_MASK) != 0)
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 040a373..f4b1e2d 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1526,6 +1526,8 @@ enum options
OPTION_NAN,
OPTION_ODD_SPREG,
OPTION_NO_ODD_SPREG,
+ OPTION_GINV,
+ OPTION_NO_GINV,
OPTION_END_OF_ENUM
};
@@ -1582,6 +1584,8 @@ struct option md_longopts[] =
{"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
{"mmips16e2", no_argument, NULL, OPTION_MIPS16E2},
{"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2},
+ {"mginv", no_argument, NULL, OPTION_GINV},
+ {"mno-ginv", no_argument, NULL, OPTION_NO_GINV},
/* Old-style architecture options. Don't add more of these. */
{"m4650", no_argument, NULL, OPTION_M4650},
@@ -1769,6 +1773,11 @@ static const struct mips_ase mips_ases[] = {
OPTION_MIPS16E2, OPTION_NO_MIPS16E2,
2, 2, -1, -1,
6 },
+
+ { "ginv", ASE_GINV, 0,
+ OPTION_GINV, OPTION_NO_GINV,
+ 6, 6, 6, 6,
+ -1 },
};
/* The set of ASEs that require -mfp64. */
@@ -2133,7 +2142,7 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
/* Clear combination ASE flags, which need to be recalculated based on
updated regular ASE settings. */
- opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT);
+ opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_GINV_VIRT);
if (enabled_p)
opts->ase |= ase->flags;
@@ -2152,6 +2161,15 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
mask |= ASE_MIPS16E2_MT;
}
+ /* The Virtualization ASE has Global INValidate (GINV)
+ instructions which are only valid when both ASEs are enabled.
+ This sets the ASE_GINV_VIRT flag when both ASEs are present. */
+ if ((opts->ase & (ASE_GINV | ASE_VIRT)) == (ASE_GINV | ASE_VIRT))
+ {
+ opts->ase |= ASE_GINV_VIRT;
+ mask |= ASE_GINV_VIRT;
+ }
+
return mask;
}
@@ -18977,6 +18995,8 @@ mips_convert_ase_flags (int ase)
ext_ases |= AFL_ASE_XPA;
if (ase & ASE_MIPS16E2)
ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0;
+ if (ase & ASE_GINV)
+ ext_ases |= AFL_ASE_GINV;
return ext_ases;
}
@@ -19988,6 +20008,9 @@ MIPS options:\n\
-mvirt generate Virtualization instructions\n\
-mno-virt do not generate Virtualization instructions\n"));
fprintf (stream, _("\
+-mginv generate Global INValidate (GINV) instructions\n\
+-mno-ginv do not generate Global INValidate instructions\n"));
+ fprintf (stream, _("\
-minsn32 only generate 32-bit microMIPS instructions\n\
-mno-insn32 generate all microMIPS instructions\n"));
fprintf (stream, _("\
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index d37a1d6..700208f 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -432,6 +432,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-mxpa}] [@b{-mno-xpa}]
[@b{-mmt}] [@b{-mno-mt}]
[@b{-mmcu}] [@b{-mno-mcu}]
+ [@b{-mginv}] [@b{-mno-ginv}]
[@b{-minsn32}] [@b{-mno-insn32}]
[@b{-mfix7000}] [@b{-mno-fix7000}]
[@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
@@ -1531,6 +1532,12 @@ Generate code for the MCU Application Specific Extension.
This tells the assembler to accept MCU instructions.
@samp{-mno-mcu} turns off this option.
+@item -mginv
+@itemx -mno-ginv
+Generate code for the Global INValidate (GINV) Application Specific
+Extension. This tells the assembler to accept GINV instructions.
+@samp{-mno-ginv} turns off this option.
+
@item -minsn32
@itemx -mno-insn32
Only use 32-bit instruction encodings when generating code for the
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index a430b0d..66b8f94 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -234,6 +234,12 @@ Generate code for the Virtualization Application Specific Extension.
This tells the assembler to accept Virtualization instructions.
@samp{-mno-virt} turns off this option.
+@item -mginv
+@itemx -mno-ginv
+Generate code for the Global INValidate (GINV) Application Specific
+Extension. This tells the assembler to accept GINV instructions.
+@samp{-mno-ginv} turns off this option.
+
@item -minsn32
@itemx -mno-insn32
Only use 32-bit instruction encodings when generating code for the
diff --git a/gas/testsuite/gas/mips/ase-errors-1.l b/gas/testsuite/gas/mips/ase-errors-1.l
index f989982..2c48f0b 100644
--- a/gas/testsuite/gas/mips/ase-errors-1.l
+++ b/gas/testsuite/gas/mips/ase-errors-1.l
@@ -40,3 +40,9 @@
# ----------------------------------------------------------------------------
.*:100: Warning: the `eva' extension requires MIPS32 revision 2 or greater
.*:103: Error: opcode not supported.* `lbue \$4,16\(\$5\)'
+# ----------------------------------------------------------------------------
+.*:108: Error: invalid operands `ginvt \$f0,\$f1'
+.*:109: Warning: the `ginv' extension requires MIPS32 revision 6 or greater
+.*:114: Error: opcode not supported.* `ginvgt \$a1,3'
+.*:116: Error: opcode not supported.* `ginvi \$a0'
+# ----------------------------------------------------------------------------
diff --git a/gas/testsuite/gas/mips/ase-errors-1.s b/gas/testsuite/gas/mips/ase-errors-1.s
index c5201c3..82eee29 100644
--- a/gas/testsuite/gas/mips/ase-errors-1.s
+++ b/gas/testsuite/gas/mips/ase-errors-1.s
@@ -102,6 +102,19 @@
.set noeva
lbue $4,16($5) # ERROR: eva not enabled
+ .set mips32r6
+ .set ginv # OK
+ ginvi $a0 # OK
+ ginvt $f0,$f1 # ERROR: Invalid operands
+ .set mips32r5 # ERROR: too low
+ ginvt $a0,1 # OK
+ .set virt
+ ginvgt $a0, 2 # OK
+ .set novirt
+ ginvgt $a1, 3 # ERROR: virt not enabled
+ .set noginv
+ ginvi $a0 # ERROR: crypto not enabled
+
# There should be no errors after this.
.set fp=32
.set mips1
diff --git a/gas/testsuite/gas/mips/ase-errors-2.l b/gas/testsuite/gas/mips/ase-errors-2.l
index 4c24690..b29c858 100644
--- a/gas/testsuite/gas/mips/ase-errors-2.l
+++ b/gas/testsuite/gas/mips/ase-errors-2.l
@@ -32,3 +32,9 @@
# ----------------------------------------------------------------------------
.*:84: Warning: the `eva' extension requires MIPS64 revision 2 or greater
.*:87: Error: opcode not supported.* `lbue \$4,16\(\$5\)'
+# ----------------------------------------------------------------------------
+.*:92: Error: invalid operands `ginvt \$f0,\$f1'
+.*:93: Warning: the `ginv' extension requires MIPS64 revision 6 or greater
+.*:98: Error: opcode not supported.* `ginvgt \$a1,3'
+.*:100: Error: opcode not supported.* `ginvi \$a0'
+# ----------------------------------------------------------------------------
diff --git a/gas/testsuite/gas/mips/ase-errors-2.s b/gas/testsuite/gas/mips/ase-errors-2.s
index 4a17e4f..1312eb0 100644
--- a/gas/testsuite/gas/mips/ase-errors-2.s
+++ b/gas/testsuite/gas/mips/ase-errors-2.s
@@ -86,6 +86,19 @@
.set noeva
lbue $4,16($5) # ERROR: eva not enabled
+ .set mips64r6
+ .set ginv # OK
+ ginvi $a0 # OK
+ ginvt $f0,$f1 # ERROR: Invalid operands
+ .set mips64r5 # ERROR: too low
+ ginvt $a0,1 # OK
+ .set virt
+ ginvgt $a0, 2 # OK
+ .set novirt
+ ginvgt $a1, 3 # ERROR: virt not enabled
+ .set noginv
+ ginvi $a0 # ERROR: crypto not enabled
+
# There should be no errors after this.
.set fp=32
.set mips4
diff --git a/gas/testsuite/gas/mips/ginv-dis.d b/gas/testsuite/gas/mips/ginv-dis.d
new file mode 100644
index 0000000..4738b5d
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv-dis.d
@@ -0,0 +1,15 @@
+#objdump: -Mginv -d --show-raw-insn
+#name: MIPS Global INValidate instructions disassembly
+#as: -mginv
+#source: ginv.s
+
+# Check MIPS Global INValidate instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+00000000 <test>:
+ 0: 7c40003d ginvi v0
+ 4: 7c6000bd ginvt v1,0x0
+ 8: 7c8001bd ginvt a0,0x1
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/ginv-error.l b/gas/testsuite/gas/mips/ginv-error.l
new file mode 100644
index 0000000..75e60e8
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv-error.l
@@ -0,0 +1,2 @@
+.*ginv-error.s: Assembler messages:
+.*ginv-error.s:3: Warning: the `ginv' extension requires MIPS32 revision 6 or greater
diff --git a/gas/testsuite/gas/mips/ginv-error.s b/gas/testsuite/gas/mips/ginv-error.s
new file mode 100644
index 0000000..1739be8
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv-error.s
@@ -0,0 +1,8 @@
+ .text
+test:
+ ginvi $2
+ ginvt $3,0
+ ginvt $4,1
+
+ .align 2
+ .space 8
diff --git a/gas/testsuite/gas/mips/ginv-virt-dis.d b/gas/testsuite/gas/mips/ginv-virt-dis.d
new file mode 100644
index 0000000..bd07a3b
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv-virt-dis.d
@@ -0,0 +1,17 @@
+#objdump: -Mginv -Mvirt -d --show-raw-insn
+#name: MIPS GINV+VIRT disassembly
+#as: --defsym VX=1 -mginv -mvirt
+#source: ginv.s
+
+# Check MIPS Global INValidate Virtualization disassembly
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+00000000 <test>:
+ 0: 7c40003d ginvi v0
+ 4: 7c6000bd ginvt v1,0x0
+ 8: 7c8001bd ginvt a0,0x1
+ c: 7ca002fd ginvgt a1,0x2
+ 10: 7cc003fd ginvgt a2,0x3
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/ginv-virt-error.l b/gas/testsuite/gas/mips/ginv-virt-error.l
new file mode 100644
index 0000000..9fe7a30
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv-virt-error.l
@@ -0,0 +1,3 @@
+.*ginv-virt-error.s: Assembler messages:
+.*ginv-virt-error.s:6: Error: opcode not supported on this processor: mips32r6 \(mips32r6\) `ginvgt \$5,2'
+.*ginv-virt-error.s:7: Error: opcode not supported on this processor: mips32r6 \(mips32r6\) `ginvgt \$6,3'
diff --git a/gas/testsuite/gas/mips/ginv-virt-error.s b/gas/testsuite/gas/mips/ginv-virt-error.s
new file mode 100644
index 0000000..b9a201b
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv-virt-error.s
@@ -0,0 +1,10 @@
+ .text
+test:
+ ginvi $2
+ ginvt $3,0
+ ginvt $4,1
+ ginvgt $5,2
+ ginvgt $6,3
+
+ .align 2
+ .space 8
diff --git a/gas/testsuite/gas/mips/ginv-virt.d b/gas/testsuite/gas/mips/ginv-virt.d
new file mode 100644
index 0000000..6390dc8
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv-virt.d
@@ -0,0 +1,17 @@
+#objdump: -d --show-raw-insn
+#name: MIPS Global INValidate Virtualization instructions
+#as: --defsym VX= -mginv -mvirt
+#source: ginv.s
+
+# Check MIPS Global INValidate Virtualization instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+00000000 <test>:
+ 0: 7c40003d ginvi v0
+ 4: 7c6000bd ginvt v1,0x0
+ 8: 7c8001bd ginvt a0,0x1
+ c: 7ca002fd ginvgt a1,0x2
+ 10: 7cc003fd ginvgt a2,0x3
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/ginv.d b/gas/testsuite/gas/mips/ginv.d
new file mode 100644
index 0000000..0cc3c2d
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv.d
@@ -0,0 +1,14 @@
+#objdump: -d --show-raw-insn
+#name: MIPS Global INValidate instructions
+#as: -mginv
+
+# Check MIPS Global INValidate instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+00000000 <test>:
+ 0: 7c40003d ginvi v0
+ 4: 7c6000bd ginvt v1,0x0
+ 8: 7c8001bd ginvt a0,0x1
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/ginv.s b/gas/testsuite/gas/mips/ginv.s
new file mode 100644
index 0000000..e9f12ab
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv.s
@@ -0,0 +1,13 @@
+ .text
+test:
+ ginvi $2
+ ginvt $3,0
+ ginvt $4,1
+
+ .ifdef VX
+ ginvgt $5,2
+ ginvgt $6,3
+ .endif
+
+ .align 2
+ .space 8
diff --git a/gas/testsuite/gas/mips/micromips@ginv-dis.d b/gas/testsuite/gas/mips/micromips@ginv-dis.d
new file mode 100644
index 0000000..e2e7000
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@ginv-dis.d
@@ -0,0 +1,16 @@
+#objdump: -Mginv -d --show-raw-insn
+#name: MIPS microMIPS Global INValidate disassembly
+#as: -mginv
+#source: ginv.s
+
+# Check microMIPS Global INValidate disassembly
+
+.*: +file format .*mips.*
+
+
+Disassembly of section .text:
+00000000 <test>:
+ 0: 0002 617c ginvi v0
+ 4: 0003 717c ginvt v1,0x0
+ 8: 0004 737c ginvt a0,0x1
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromips@ginv-virt-dis.d b/gas/testsuite/gas/mips/micromips@ginv-virt-dis.d
new file mode 100644
index 0000000..c0a4acb
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@ginv-virt-dis.d
@@ -0,0 +1,17 @@
+#objdump: -mmips:isa32 -Mginv -Mvirt -d --show-raw-insn
+#name: MIPS microMIPS GINV+VIRT instruction disassembly
+#as: --defsym VX= -mginv -mvirt
+#source: ginv.s
+
+# Check microMIPS Global INValidate Virtualization disassembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <test>:
+ 0: 0002 617c ginvi v0
+ 4: 0003 717c ginvt v1,0x0
+ 8: 0004 737c ginvt a0,0x1
+ c: 0005 7d7c ginvgt a1,0x2
+ 10: 0006 7f7c ginvgt a2,0x3
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromips@ginv-virt.d b/gas/testsuite/gas/mips/micromips@ginv-virt.d
new file mode 100644
index 0000000..08889fb
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@ginv-virt.d
@@ -0,0 +1,17 @@
+#objdump: -d --show-raw-insn
+#name: MIPS microMIPS Global INValidate Virtualization instructions
+#as: --defsym VX= -mginv -mvirt
+#source: ginv.s
+
+# Check microMIPS Global INValidate Virtualization instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <test>:
+ 0: 0002 617c ginvi v0
+ 4: 0003 717c ginvt v1,0x0
+ 8: 0004 737c ginvt a0,0x1
+ c: 0005 7d7c ginvgt a1,0x2
+ 10: 0006 7f7c ginvgt a2,0x3
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromips@ginv.d b/gas/testsuite/gas/mips/micromips@ginv.d
new file mode 100644
index 0000000..e2e7000
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@ginv.d
@@ -0,0 +1,16 @@
+#objdump: -Mginv -d --show-raw-insn
+#name: MIPS microMIPS Global INValidate disassembly
+#as: -mginv
+#source: ginv.s
+
+# Check microMIPS Global INValidate disassembly
+
+.*: +file format .*mips.*
+
+
+Disassembly of section .text:
+00000000 <test>:
+ 0: 0002 617c ginvi v0
+ 4: 0003 717c ginvt v1,0x0
+ 8: 0004 737c ginvt a0,0x1
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 94c4506..8e2dbc7 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -2050,4 +2050,12 @@ if { [istarget mips*-*-vxworks*] } {
run_list_test_arches "r6-branch-constraints" "-32" \
[mips_arch_list_matching mips32r6]
+
+ run_dump_test_arches "ginv" "" [mips_arch_list_matching mips32r6]
+ run_dump_test_arches "ginv-virt" "" [mips_arch_list_matching micromipsr6]
+ run_dump_test_arches "ginv-dis" "" [mips_arch_list_matching mips32r6]
+ run_dump_test_arches "ginv-virt-dis" "" \
+ [mips_arch_list_matching micromipsr6]
+ run_list_test "ginv-error" "-mips32 -mginv"
+ run_list_test "ginv-virt-error" "-mips32r6 -mginv"
}
diff --git a/include/elf/mips.h b/include/elf/mips.h
index a4bea43..d98b312 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -1235,7 +1235,8 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */
#define AFL_ASE_DSPR3 0x00002000 /* DSP R3 ASE. */
#define AFL_ASE_MIPS16E2 0x00004000 /* MIPS16e2 ASE. */
-#define AFL_ASE_MASK 0x00007fff /* All ASEs. */
+#define AFL_ASE_GINV 0x00020000 /* GINV ASE. */
+#define AFL_ASE_MASK 0x00027fff /* All ASEs. */
/* Values for the isa_ext word of an ABI flags structure. */
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index ceae9ec..c163846 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -989,6 +989,9 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
"-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
"-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
+ GINV ASE usage:
+ "+\" 2 bit Global TLB invalidate type at bit 8
+
Other:
"()" parens surrounding optional value
"," separates operands
@@ -1294,6 +1297,11 @@ static const unsigned int mips_isa_table[] = {
/* The Virtualization ASE has eXtended Physical Addressing (XPA)
instructions which are only valid when both ASEs are enabled. */
#define ASE_XPA_VIRT 0x00020000
+/* Global INValidate Extension. */
+#define ASE_GINV 0x00800000
+/* The Virtualization ASE has Global INValidate extension instructions
+ which are only valid when both ASEs are enabled. */
+#define ASE_GINV_VIRT 0x01000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -2308,6 +2316,9 @@ extern const int bfd_mips16_num_opcodes;
"+*" 5-bit register vector element index at bit 16
"+|" 8-bit mask at bit 16
+ GINV ASE usage:
+ "+\" 2 bit Global TLB invalidate type at bit 8
+
Other:
"()" parens surrounding optional value
"," separates operands
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index d6234af..894c1f2 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -137,6 +137,7 @@ decode_micromips_operand (const char *p)
case '&': SPECIAL (0, 0, IMM_INDEX);
case '*': SPECIAL (5, 16, REG_INDEX);
case '|': BIT (8, 16, 0); /* (0 .. 255) */
+ case '\\': BIT (2, 9, 0); /* (00 .. 11) */
}
break;
@@ -284,6 +285,10 @@ decode_micromips_operand (const char *p)
#define XPA ASE_XPA
#define XPAVZ ASE_XPA_VIRT
+/* Global INValidate (GINV) support. */
+#define GINV ASE_GINV
+#define GINVVZ ASE_GINV_VIRT
+
const struct mips_opcode micromips_opcodes[] =
{
/* These instructions appear first so that the disassembler will find
@@ -1150,6 +1155,12 @@ const struct mips_opcode micromips_opcodes[] =
{"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 },
{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
+
+/* Global INValidate ASE */
+{"ginvi", "s", 0x0000617c, 0xffe0ffff, RD_1, 0, 0, GINV, 0 },
+{"ginvt", "s,+\\", 0x0000717c, 0xffe0f9ff, RD_1, 0, 0, GINV, 0 },
+{"ginvgt", "s,+\\", 0x0000797c, 0xffe0f9ff, RD_1, 0, 0, GINVVZ, 0 },
+
/* microMIPS Enhanced VA Scheme */
{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 },
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 4519500..4eb8f00 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -563,7 +563,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
ISA_MIPS32R6,
(ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
- | ASE_DSPR2 | ASE_DSPR3),
+ | ASE_DSPR2 | ASE_DSPR3 | ASE_GINV),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -602,7 +602,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6,
ISA_MIPS64R6,
(ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
- | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3),
+ | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_GINV),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -817,6 +817,8 @@ mips_calculate_combination_ases (unsigned long opcode_ases)
if ((opcode_ases & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT))
combination_ases |= ASE_XPA_VIRT;
+ if ((opcode_ases & (ASE_GINV | ASE_VIRT)) == (ASE_GINV | ASE_VIRT))
+ combination_ases |= ASE_GINV_VIRT;
if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
combination_ases |= ASE_MIPS16E2_MT;
return combination_ases;
@@ -900,6 +902,12 @@ set_default_mips_dis_options (struct disassemble_info *info)
static bfd_boolean
parse_mips_ase_option (const char *option)
{
+ if (CONST_STRNEQ (option, "ginv"))
+ {
+ mips_ase |= ASE_GINV;
+ return TRUE;
+ }
+
if (CONST_STRNEQ (option, "msa"))
{
mips_ase |= ASE_MSA;
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 19fca40..ee8b3b7 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -139,6 +139,7 @@ decode_mips_operand (const char *p)
case '\'': BRANCH (26, 0, 2);
case '"': BRANCH (21, 0, 2);
case ';': SPECIAL (10, 16, SAME_RS_RT);
+ case '\\': BIT (2, 8, 0); /* (00 .. 11) */
}
break;
@@ -404,6 +405,10 @@ decode_mips_operand (const char *p)
#define XPA ASE_XPA
#define XPAVZ ASE_XPA_VIRT
+/* Global INValidate (GINV) support. */
+#define GINV ASE_GINV
+#define GINVVZ ASE_GINV_VIRT
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
@@ -3275,6 +3280,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"jalrc", "t", 0xf8000000, 0xffe0ffff, RD_1|NODS, 0, I37, 0, 0 },
{"jialc", "t,j", 0xf8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 },
+{"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 },
+{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 },
+{"ginvgt", "s,+\\", 0x7c0000fd, 0xfc1ffcff, RD_1, 0, 0, GINVVZ, 0 },
+
{"cmp.af.s", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
{"cmp.af.d", "D,S,T", 0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
{"cmp.eq.s", "D,S,T", 0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
--
2.9.5