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Re: [PATCH] x86: correct UDn


On Mon, Nov 20, 2017 at 5:38 AM, Jan Beulich <JBeulich@suse.com> wrote:
> Make the assembler recognize UD0, supporting both forms. The disassembler
> obviously has to pick one of the two - use the modern form here.
>
> Make assembler and disassembler properly emit / expect a ModR/M byte for
> UD1.
>
> For the testsuite, as arch-4 already tests all UDn, avoid producing a
> huge delta for other tests using UD2B by making them use UD2 instead.
>
> gas/
> 2017-11-20  Jan Beulich  <jbeulich@suse.com>
>
>         * testsuite/gas/i386/arch-4.s: Correct ud1 and ud2b. Add ud0.
>         * testsuite/gas/i386/intel.s: Test ud2 instead of ud2b.
>         * testsuite/gas/i386/opcode.s: Likewise.
>         * testsuite/gas/i386/arch-4.d, testsuite/gas/i386/intel.d,
>         testsuite/gas/i386/opcode.d, testsuite/gas/i386/opcode-intel.d,
>         testsuite/gas/i386/opcode-suffix.d: Adjust expectations.
>
> opcodes/
> 2017-11-20  Jan Beulich  <jbeulich@suse.com>
>
>         * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
>         (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
>         * i386-opc.tbl (ud1, ud2b): Add operands.
>         (ud0): New.
>         * i386-tbl.h: Re-generate.
>
> --- a/gas/testsuite/gas/i386/arch-4.d
> +++ b/gas/testsuite/gas/i386/arch-4.d
> @@ -1,4 +1,3 @@
> -#as: -march=generic32
>  #objdump: -dw
>  #name: i386 arch 4
>
> @@ -7,8 +6,10 @@
>  Disassembly of section .text:
>
>  0+ <.text>:
> -[      ]*[a-f0-9]+:    0f b9                   ud1
> +[      ]*[a-f0-9]+:    0f ff cc [      ]*ud0    %esp,%ecx
> +[      ]*[a-f0-9]+:    0f ff 07 [      ]*ud0    \(%edi\),%eax
> +[      ]*[a-f0-9]+:    0f b9 07 [      ]*ud1    \(%edi\),%eax
>  [      ]*[a-f0-9]+:    0f 0b                   ud2
>  [      ]*[a-f0-9]+:    0f 0b                   ud2
> -[      ]*[a-f0-9]+:    0f b9                   ud1
> +[      ]*[a-f0-9]+:    0f b9 07 [      ]*ud1    \(%edi\),%eax
>  #pass
> --- a/gas/testsuite/gas/i386/arch-4.s
> +++ b/gas/testsuite/gas/i386/arch-4.s
> @@ -1,5 +1,7 @@
>         .text
> -       ud1
> +       ud0; int3
> +       ud0     (%edi),%eax
> +       ud1     (%edi),%eax
>         ud2
>         ud2a
> -       ud2b
> +       ud2b    (%edi),%eax
> --- a/gas/testsuite/gas/i386/intel.d
> +++ b/gas/testsuite/gas/i386/intel.d
> @@ -360,7 +360,7 @@ Disassembly of section .text:
>  [      ]*[a-f0-9]+:    0f b5 90 90 90 90 90 [  ]*lgs    -0x6f6f6f70\(%eax\),%edx
>  [      ]*[a-f0-9]+:    0f b6 90 90 90 90 90 [  ]*movzbl -0x6f6f6f70\(%eax\),%edx
>  [      ]*[a-f0-9]+:    0f b7 90 90 90 90 90 [  ]*movzwl -0x6f6f6f70\(%eax\),%edx
> -[      ]*[a-f0-9]+:    0f b9 [         ]*ud1
> +[      ]*[a-f0-9]+:    0f 0b [         ]*ud2[  ]*
>  [      ]*[a-f0-9]+:    0f bb 90 90 90 90 90 [  ]*btc    %edx,-0x6f6f6f70\(%eax\)
>  [      ]*[a-f0-9]+:    0f bc 90 90 90 90 90 [  ]*bsf    -0x6f6f6f70\(%eax\),%edx
>  [      ]*[a-f0-9]+:    0f bd 90 90 90 90 90 [  ]*bsr    -0x6f6f6f70\(%eax\),%edx
> --- a/gas/testsuite/gas/i386/intel.s
> +++ b/gas/testsuite/gas/i386/intel.s
> @@ -353,7 +353,7 @@ foo:
>   lgs    edx, 0x90909090[eax]
>   movzx  edx, byte ptr 0x90909090[eax]
>   movzx  edx, word ptr 0x90909090[eax]
> - ud2b
> + ud2
>   btc    0x90909090[eax], edx
>   bsf    edx, 0x90909090[eax]
>   bsr    edx, 0x90909090[eax]
> --- a/gas/testsuite/gas/i386/opcode-intel.d
> +++ b/gas/testsuite/gas/i386/opcode-intel.d
> @@ -358,7 +358,7 @@ Disassembly of section .text:
>   *[0-9a-f]+:   0f b5 90 90 90 90 90[   ]+lgs[  ]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\]
>   *[0-9a-f]+:   0f b6 90 90 90 90 90[   ]+movzx[        ]+edx,BYTE PTR \[eax-0x6f6f6f70\]
>   *[0-9a-f]+:   0f b7 90 90 90 90 90[   ]+movzx[        ]+edx,WORD PTR \[eax-0x6f6f6f70\]
> - *[0-9a-f]+:   0f b9[  ]+ud1[  ]*
> + *[0-9a-f]+:   0f 0b[  ]+ud2[  ]*
>   *[0-9a-f]+:   0f bb 90 90 90 90 90[   ]+btc[  ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
>   *[0-9a-f]+:   0f bc 90 90 90 90 90[   ]+bsf[  ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
>   *[0-9a-f]+:   0f bd 90 90 90 90 90[   ]+bsr[  ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
> --- a/gas/testsuite/gas/i386/opcode-suffix.d
> +++ b/gas/testsuite/gas/i386/opcode-suffix.d
> @@ -358,7 +358,7 @@ Disassembly of section .text:
>   *[0-9a-f]+:   0f b5 90 90 90 90 90[   ]+lgsl[         ]+-0x6f6f6f70\(%eax\),%edx
>   *[0-9a-f]+:   0f b6 90 90 90 90 90[   ]+movzbl -0x6f6f6f70\(%eax\),%edx
>   *[0-9a-f]+:   0f b7 90 90 90 90 90[   ]+movzwl -0x6f6f6f70\(%eax\),%edx
> - *[0-9a-f]+:   0f b9[  ]+ud1[  ]+
> + *[0-9a-f]+:   0f 0b[  ]+ud2[  ]*
>   *[0-9a-f]+:   0f bb 90 90 90 90 90[   ]+btcl[         ]+%edx,-0x6f6f6f70\(%eax\)
>   *[0-9a-f]+:   0f bc 90 90 90 90 90[   ]+bsfl[         ]+-0x6f6f6f70\(%eax\),%edx
>   *[0-9a-f]+:   0f bd 90 90 90 90 90[   ]+bsrl[         ]+-0x6f6f6f70\(%eax\),%edx
> --- a/gas/testsuite/gas/i386/opcode.d
> +++ b/gas/testsuite/gas/i386/opcode.d
> @@ -357,7 +357,7 @@ Disassembly of section .text:
>   57e:  0f b5 90 90 90 90 90 [  ]*lgs    -0x6f6f6f70\(%eax\),%edx
>   585:  0f b6 90 90 90 90 90 [  ]*movzbl -0x6f6f6f70\(%eax\),%edx
>   58c:  0f b7 90 90 90 90 90 [  ]*movzwl -0x6f6f6f70\(%eax\),%edx
> - 593:  0f b9 [         ]*ud1
> + 593:  0f 0b [         ]*ud2[  ]*
>   595:  0f bb 90 90 90 90 90 [  ]*btc    %edx,-0x6f6f6f70\(%eax\)
>   59c:  0f bc 90 90 90 90 90 [  ]*bsf    -0x6f6f6f70\(%eax\),%edx
>   5a3:  0f bd 90 90 90 90 90 [  ]*bsr    -0x6f6f6f70\(%eax\),%edx
> --- a/gas/testsuite/gas/i386/opcode.s
> +++ b/gas/testsuite/gas/i386/opcode.s
> @@ -350,7 +350,7 @@ foo:
>   lgs    0x90909090(%eax),%edx
>   movzbl 0x90909090(%eax),%edx
>   movzwl 0x90909090(%eax),%edx
> - ud2b
> + ud2
>   btc    %edx,0x90909090(%eax)
>   bsf    0x90909090(%eax),%edx
>   bsr    0x90909090(%eax),%edx
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -3067,7 +3067,7 @@ static const struct dis386 dis386_twobyt
>    { "movz{wR|x}",      { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
>    /* b8 */
>    { PREFIX_TABLE (PREFIX_0FB8) },
> -  { "ud1",             { XX }, 0 },
> +  { "ud1S",            { Gv, Ev }, 0 },
>    { REG_TABLE (REG_0FBA) },
>    { "btcS",            { Evh1, Gv }, 0 },
>    { PREFIX_TABLE (PREFIX_0FBC) },
> @@ -3145,7 +3145,7 @@ static const struct dis386 dis386_twobyt
>    { "paddb",           { MX, EM }, PREFIX_OPCODE },
>    { "paddw",           { MX, EM }, PREFIX_OPCODE },
>    { "paddd",           { MX, EM }, PREFIX_OPCODE },
> -  { Bad_Opcode },
> +  { "ud0S",            { Gv, Ev }, 0 },
>  };
>
>  static const unsigned char onebyte_has_modrm[256] = {
> @@ -3185,11 +3185,11 @@ static const unsigned char twobyte_has_m
>    /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
>    /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
>    /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
> -  /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
> +  /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
>    /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
>    /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
>    /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
> -  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
> +  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
>    /*       -------------------------------        */
>    /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
>  };
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -862,9 +862,12 @@ ud2, 0, 0xf0b, None, 2, Cpu186, No_bSuf|
>  // alias for ud2
>  ud2a, 0, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
>  // 2nd. official undefined instr.
> -ud1, 0, 0xfb9, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
> +ud1, 2, 0xfb9, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
>  // alias for ud1
> -ud2b, 0, 0xfb9, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
> +ud2b, 2, 0xfb9, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
> +// 3rd official undefined instr
> +ud0, 0, 0xfff, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

Do we really need this?  It will confuse disassembler.

> +ud0, 2, 0xfff, None, 2, CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }

Where does CpuSSE4_2 come from?

>  cmovo, 2, 0xf40, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
>  cmovno, 2, 0xf41, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
>
>



-- 
H.J.


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