This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
RE: [PATCH 1/6] Enable Intel AVX512_VBMI2 instructions
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: "Igor V Tsimbalist" <igor dot v dot tsimbalist at intel dot com>
- Cc: "Hongjiu Lu" <hongjiu dot lu at intel dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Mon, 20 Nov 2017 01:07:07 -0700
- Subject: RE: [PATCH 1/6] Enable Intel AVX512_VBMI2 instructions
- Authentication-results: sourceware.org; auth=none
- References: <D511F25789BA7F4EBA64C8A63891A00291F4626C@IRSMSX102.ger.corp.intel.com> <D511F25789BA7F4EBA64C8A63891A00291F4646B@IRSMSX102.ger.corp.intel.com>
>>> On 21.10.17 at 11:15, <igor.v.tsimbalist@intel.com> wrote:
> Resending the patch after regenerated files removal (mailer-daemon
> complained about the size of the patch).
What's the point of the Vec_Disp8 ...
>+vpcompressb, 2, 0x6663, None, 1, CpuAVX512_VBMI2, Modrm|EVex=1|Masking=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
>+vpcompressb, 2, 0x6663, None, 1, CpuAVX512_VBMI2|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
>+vpcompressb, 2, 0x6663, None, 1, CpuAVX512_VBMI2|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
... here and ...
>+vpexpandb, 2, 0x6662, None, 1, CpuAVX512_VBMI2, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
>+vpexpandb, 2, 0x6662, None, 1, CpuAVX512_VBMI2|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
>+vpexpandb, 2, 0x6662, None, 1, CpuAVX512_VBMI2|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
? There's no Disp8 scaling here. Vec_Disp8 really is mostly (and
perhaps entirely, i.e. I'm in the process of determining whether we
can get rid of it) redundant with Disp8MemShift beng non-zero.
Also what was the point of inserting a stray blank line at the top
of opcodes/i386-opc.tbl?
Jan