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Re: [PATCH] [PowerPC VLE] Add LSP instructions support
Hello Alan
Please find attached new version.
BTW I found some mess with tabs and spaces in ppc-opc.c
Here I see tabs+spaces:
static long
extract_dm (unsigned long insn,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
int *invalid)
meanwhile here is only only spaces:
static unsigned long
insert_vlesi (unsigned long insn,
long value,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
const char **errmsg ATTRIBUTE_UNUSED)
Which one is correct ?
Alex
On Mon, Aug 21, 2017 at 12:37 PM, Alan Modra <amodra@gmail.com> wrote:
> On Sun, Aug 20, 2017 at 12:15:11AM +0300, Alexander Fedotov wrote:
>> This patch adds LSP instructions support to PowerPC VLE. Based against
>> current master branch.
>
> This is OK with a few fixes.
>
>> +2017-08-19 Alexander Fedotov <alexander.fedotov@nxp.com>
>> + Edmar Wienskoski <edmar.wienskoski@nxp.com
>> +
>> + *gas/testsuite/gas/ppc/lsp-checks.d: New test
>> + *gas/testsuite/gas/ppc/lsp-checks.l: New
>> + *gas/testsuite/gas/ppc/lsp-checks.s: New
>> + *gas/testsuite/gas/ppc/lsp.d: New
>> + *gas/testsuite/gas/ppc/lsp.s: New
>> + *gas/testsuite/gas/ppc/ppc.exp: Run new tests.
>> +
>
> Files in a ChangeLog should be relative to the ChangeLog, and there
> should be a space after the '*'.
>
>> +static unsigned long
>> +insert_evuimm2_ex0 (unsigned long insn,
>> + long value,
>> + ppc_cpu_t dialect ATTRIBUTE_UNUSED,
>> + const char **errmsg)
>
> Formatting here and on other new functions is broken. It should be
>
> static unsigned long
> insert_evuimm2_ex0 (unsigned long insn,
> long value,
> ppc_cpu_t dialect ATTRIBUTE_UNUSED,
> const char **errmsg)
>
> Maybe the tabs were eaten by your email client? There are other minor
> whitespace issue too. If you add the following to you binutils
> .git/config under the [core] heading, git will show them to you
>
> whitespace = indent-with-non-tab,space-before-tab,trailing-space
>
> --
> Alan Modra
> Australia Development Lab, IBM
--
Best regards,
AF
From a1e1d240580c569d4dbfd4cd6f95c7bdfb28da95 Mon Sep 17 00:00:00 2001
From: Alexander Fedotov-B55613 <b55613@freescale.com>
Date: Mon, 21 Aug 2017 13:02:13 +0300
Subject: [PATCH] [PowerPC VLE] Add LSP (Lightweight Signal Processing) instructions support
---
gas/ChangeLog | 10 +
gas/testsuite/gas/ppc/lsp-checks.d | 3 +
gas/testsuite/gas/ppc/lsp-checks.l | 92 ++++
gas/testsuite/gas/ppc/lsp-checks.s | 112 +++++
gas/testsuite/gas/ppc/lsp.d | 687 ++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/lsp.s | 694 +++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/ppc.exp | 5 +
include/ChangeLog | 5 +
include/opcode/ppc.h | 3 +
opcodes/ChangeLog | 35 ++
opcodes/ppc-dis.c | 2 +-
opcodes/ppc-opc.c | 890 ++++++++++++++++++++++++++++++++++++-
12 files changed, 2532 insertions(+), 6 deletions(-)
create mode 100644 gas/testsuite/gas/ppc/lsp-checks.d
create mode 100644 gas/testsuite/gas/ppc/lsp-checks.l
create mode 100644 gas/testsuite/gas/ppc/lsp-checks.s
create mode 100644 gas/testsuite/gas/ppc/lsp.d
create mode 100644 gas/testsuite/gas/ppc/lsp.s
diff --git a/gas/ChangeLog b/gas/ChangeLog
index cdfa036..b8b7307 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2017-08-19 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com
+
+ * gas/testsuite/gas/ppc/lsp-checks.d: New test
+ * gas/testsuite/gas/ppc/lsp-checks.l: New
+ * gas/testsuite/gas/ppc/lsp-checks.s: New
+ * gas/testsuite/gas/ppc/lsp.d: New
+ * gas/testsuite/gas/ppc/lsp.s: New
+ * gas/testsuite/gas/ppc/ppc.exp: Run new tests.
+
2017-08-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/tc-aarch64.c (REGDEF_ALIAS): Define
diff --git a/gas/testsuite/gas/ppc/lsp-checks.d b/gas/testsuite/gas/ppc/lsp-checks.d
new file mode 100644
index 0000000..a91e09d
--- /dev/null
+++ b/gas/testsuite/gas/ppc/lsp-checks.d
@@ -0,0 +1,3 @@
+#name: Test LSP operands checks
+#as: -mvle
+#error-output: lsp-checks.l
diff --git a/gas/testsuite/gas/ppc/lsp-checks.l b/gas/testsuite/gas/ppc/lsp-checks.l
new file mode 100644
index 0000000..db2eff7
--- /dev/null
+++ b/gas/testsuite/gas/ppc/lsp-checks.l
@@ -0,0 +1,92 @@
+[^:]*: Assembler messages:
+[^:]*:22: Error: invalid offset
+[^:]*:23: Error: UIMM values >15 are illegal
+[^:]*:24: Error: UIMM values >15 are illegal
+[^:]*:25: Error: UIMM values >15 are illegal
+[^:]*:26: Error: UIMM values >15 are illegal
+[^:]*:27: Error: UIMM values >15 are illegal
+[^:]*:28: Error: UIMM values >15 are illegal
+[^:]*:29: Error: GPR odd is illegal
+[^:]*:30: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:31: Error: GPR odd is illegal
+[^:]*:32: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:33: Error: GPR odd is illegal
+[^:]*:34: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:35: Error: GPR odd is illegal
+[^:]*:36: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:37: Error: GPR odd is illegal
+[^:]*:38: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:39: Error: GPR odd is illegal
+[^:]*:40: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:41: Error: GPR odd is illegal
+[^:]*:42: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:43: Error: GPR odd is illegal
+[^:]*:44: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:45: Error: GPR odd is illegal
+[^:]*:46: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:47: Error: GPR odd is illegal
+[^:]*:48: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:49: Error: GPR odd is illegal
+[^:]*:50: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:51: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:52: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:53: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:54: Error: GPR odd is illegal
+[^:]*:55: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:56: Error: GPR odd is illegal
+[^:]*:57: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:58: Error: GPR odd is illegal
+[^:]*:59: Error: operand out of domain \(7 is not a multiple of 8\)
+[^:]*:60: Error: GPR odd is illegal
+[^:]*:61: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:62: Error: GPR odd is illegal
+[^:]*:63: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:64: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:65: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:66: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:67: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:68: Error: operand out of domain \(3 is not a multiple of 2\)
+[^:]*:69: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:70: Error: operand out of domain \(3 is not a multiple of 4\)
+[^:]*:71: Error: GPR odd is illegal
+[^:]*:72: Error: UIMM = 00000 is illegal
+[^:]*:73: Error: GPR odd is illegal
+[^:]*:74: Error: UIMM = 00000 is illegal
+[^:]*:75: Error: GPR odd is illegal
+[^:]*:76: Error: UIMM = 00000 is illegal
+[^:]*:77: Error: GPR odd is illegal
+[^:]*:78: Error: UIMM = 00000 is illegal
+[^:]*:79: Error: GPR odd is illegal
+[^:]*:80: Error: UIMM = 00000 is illegal
+[^:]*:81: Error: GPR odd is illegal
+[^:]*:82: Error: UIMM = 00000 is illegal
+[^:]*:83: Error: GPR odd is illegal
+[^:]*:84: Error: UIMM = 00000 is illegal
+[^:]*:85: Error: GPR odd is illegal
+[^:]*:86: Error: UIMM = 00000 is illegal
+[^:]*:87: Error: GPR odd is illegal
+[^:]*:88: Error: UIMM = 00000 is illegal
+[^:]*:89: Error: GPR odd is illegal
+[^:]*:90: Error: UIMM = 00000 is illegal
+[^:]*:91: Error: GPR odd is illegal
+[^:]*:92: Error: UIMM = 00000 is illegal
+[^:]*:93: Error: UIMM = 00000 is illegal
+[^:]*:94: Error: UIMM = 00000 is illegal
+[^:]*:95: Error: UIMM = 00000 is illegal
+[^:]*:96: Error: UIMM = 00000 is illegal
+[^:]*:97: Error: UIMM = 00000 is illegal
+[^:]*:98: Error: GPR odd is illegal
+[^:]*:99: Error: UIMM = 00000 is illegal
+[^:]*:100: Error: GPR odd is illegal
+[^:]*:101: Error: UIMM = 00000 is illegal
+[^:]*:102: Error: GPR odd is illegal
+[^:]*:103: Error: UIMM = 00000 is illegal
+[^:]*:104: Error: GPR odd is illegal
+[^:]*:105: Error: UIMM = 00000 is illegal
+[^:]*:106: Error: UIMM = 00000 is illegal
+[^:]*:107: Error: UIMM = 00000 is illegal
+[^:]*:108: Error: UIMM = 00000 is illegal
+[^:]*:109: Error: UIMM = 00000 is illegal
+[^:]*:110: Error: UIMM = 00000 is illegal
+[^:]*:111: Error: UIMM = 00000 is illegal
+[^:]*:112: Error: UIMM = 00000 is illegal
diff --git a/gas/testsuite/gas/ppc/lsp-checks.s b/gas/testsuite/gas/ppc/lsp-checks.s
new file mode 100644
index 0000000..479eede
--- /dev/null
+++ b/gas/testsuite/gas/ppc/lsp-checks.s
@@ -0,0 +1,112 @@
+# Test PA LSP operands checks
+ .section ".text"
+
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0 ;# ok
+ .equ rD_odd, 1 ;# GPR odd is illegal
+ .equ rS,0 ;# ok
+ .equ rS_odd, 1 ;# GPR odd is illegal
+ .equ UIMM_GT15, 16 ;# UIMM values >15 are illegal
+ .equ UIMM_2, 2 ;# ok
+ .equ UIMM_2_ILL, 3 ;# 3 is not a multiple of 2
+ .equ UIMM_2_ZERO, 0 ;# UIMM = 00000 is illegal if U=1
+ .equ UIMM_4, 4 ;# ok
+ .equ UIMM_4_ILL, 3 ;# 3 is not a multiple of 4
+ .equ UIMM_4_ZERO, 0 ;# UIMM = 00000 is illegal if U=1
+ .equ UIMM_8, 8 ;# ok
+ .equ UIMM_8_ILL, 7 ;# 7 is not a multiple of 8
+ .equ UIMM_8_ZERO, 0 ;# UIMM = 00000 is illegal if U=1
+ .equ offset, 0 ;# invalid offset
+
+ zxtrw rD, rA, rB, offset
+ zvsrhiu rD, rA, UIMM_GT15
+ zvsrhis rD, rA, UIMM_GT15
+ zvslhi rD, rA, UIMM_GT15
+ zvrlhi rD, rA, UIMM_GT15
+ zvslhius rD, rA, UIMM_GT15
+ zvslhiss rD, rA, UIMM_GT15
+ zldd rD_odd, UIMM_8(rA)
+ zldd rD, UIMM_8_ILL(rA)
+ zldw rD_odd, UIMM_8(rA)
+ zldw rD, UIMM_8_ILL(rA)
+ zldh rD_odd, UIMM_8(rA)
+ zldh rD, UIMM_8_ILL(rA)
+ zlwgsfd rD_odd, UIMM_4(rA)
+ zlwgsfd rD, UIMM_4_ILL(rA)
+ zlwwosd rD_odd, UIMM_4(rA)
+ zlwwosd rD, UIMM_4_ILL(rA)
+ zlwhsplatwd rD_odd, UIMM_4(rA)
+ zlwhsplatwd rD, UIMM_4_ILL(rA)
+ zlwhsplatd rD_odd, UIMM_4(rA)
+ zlwhsplatd rD, UIMM_4_ILL(rA)
+ zlwhgwsfd rD_odd, UIMM_4(rA)
+ zlwhgwsfd rD, UIMM_4_ILL(rA)
+ zlwhed rD_odd, UIMM_4(rA)
+ zlwhed rD, UIMM_4_ILL(rA)
+ zlwhosd rD_odd, UIMM_4(rA)
+ zlwhosd rD, UIMM_4_ILL(rA)
+ zlwhoud rD_odd, UIMM_4(rA)
+ zlwh rD, UIMM_4_ILL(rA)
+ zlww rD, UIMM_4_ILL(rA)
+ zlhgwsf rD, UIMM_2_ILL(rA)
+ zlhhsplat rD, UIMM_2_ILL(rA)
+ zstdd rS_odd, UIMM_8(rA)
+ zstdd rS, UIMM_8_ILL(rA)
+ zstdw rS_odd, UIMM_8(rA)
+ zstdw rS, UIMM_8_ILL(rA)
+ zstdh rS_odd, UIMM_8(rA)
+ zstdh rS, UIMM_8_ILL(rA)
+ zstwhed rS_odd, UIMM_4(rA)
+ zstwhed rS, UIMM_4_ILL(rA)
+ zstwhod rS_odd, UIMM_4(rA)
+ zstwhod rS, UIMM_4_ILL(rA)
+ zlhhe rD, UIMM_2_ILL(rA)
+ zlhhos rD, UIMM_2_ILL(rA)
+ zlhhou rD, UIMM_2_ILL(rA)
+ zsthe rS, UIMM_2_ILL(rA)
+ zstho rS, UIMM_2_ILL(rA)
+ zstwh rS, UIMM_4_ILL(rA)
+ zstww rS, UIMM_4_ILL(rA)
+ zlddu rD_odd, UIMM_8(rA)
+ zlddu rD, UIMM_8_ZERO(rA)
+ zldwu rD_odd, UIMM_8(rA)
+ zldwu rD, UIMM_8_ZERO(rA)
+ zldhu rD_odd, UIMM_8(rA)
+ zldhu rD, UIMM_8_ZERO(rA)
+ zlwgsfdu rD_odd, UIMM_4(rA)
+ zlwgsfdu rD, UIMM_4_ZERO(rA)
+ zlwwosdu rD_odd, UIMM_4(rA)
+ zlwwosdu rD, UIMM_4_ZERO(rA)
+ zlwhsplatwdu rD_odd, UIMM_4(rA)
+ zlwhsplatwdu rD, UIMM_4_ZERO(rA)
+ zlwhsplatdu rD_odd, UIMM_4(rA)
+ zlwhsplatdu rD, UIMM_4_ZERO(rA)
+ zlwhgwsfdu rD_odd, UIMM_4(rA)
+ zlwhgwsfdu rD, UIMM_4_ZERO(rA)
+ zlwhedu rD_odd, UIMM_4(rA)
+ zlwhedu rD, UIMM_4_ZERO(rA)
+ zlwhosdu rD_odd, UIMM_4(rA)
+ zlwhosdu rD, UIMM_4_ZERO(rA)
+ zlwhoudu rD_odd, UIMM_4(rA)
+ zlwhoudu rD, UIMM_4_ZERO(rA)
+ zlwhu rD, UIMM_4_ZERO(rA)
+ zlwwu rD, UIMM_4_ZERO(rA)
+ zlhgwsfu rD, UIMM_2_ZERO(rA)
+ zlhhsplatu rD, UIMM_2_ZERO(rA)
+ zstddu rS, UIMM_8_ZERO(rA)
+ zstdwu rS_odd, UIMM_8(rA)
+ zstdwu rS, UIMM_8_ZERO(rA)
+ zstdhu rS_odd, UIMM_8(rA)
+ zstdhu rS, UIMM_8_ZERO(rA)
+ zstwhedu rS_odd, UIMM_4(rA)
+ zstwhedu rS, UIMM_4_ZERO(rA)
+ zstwhodu rS_odd, UIMM_4(rA)
+ zstwhodu rS, UIMM_4_ZERO(rA)
+ zlhheu rD, UIMM_2_ZERO(rA)
+ zlhhosu rD, UIMM_2_ZERO(rA)
+ zlhhouu rD, UIMM_2_ZERO(rA)
+ zstheu rS, UIMM_2_ZERO(rA)
+ zsthou rS, UIMM_2_ZERO(rA)
+ zstwhu rS, UIMM_4_ZERO(rA)
+ zstwwu rS, UIMM_4_ZERO(rA)
diff --git a/gas/testsuite/gas/ppc/lsp.d b/gas/testsuite/gas/ppc/lsp.d
new file mode 100644
index 0000000..c9fb476
--- /dev/null
+++ b/gas/testsuite/gas/ppc/lsp.d
@@ -0,0 +1,687 @@
+#as: -mvle
+#objdump: -d -Mvle
+#name: Validate LSP instructions
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 10 01 7a 00 zvaddih r0,r1,15
+ 4: 10 01 7a 01 zvsubifh r0,r1,15
+ 8: 10 01 12 04 zvaddh r0,r1,r2
+ c: 10 01 12 05 zvsubfh r0,r1,r2
+ 10: 10 01 12 06 zvaddsubfh r0,r1,r2
+ 14: 10 01 12 07 zvsubfaddh r0,r1,r2
+ 18: 10 01 12 0c zvaddhx r0,r1,r2
+ 1c: 10 01 12 0d zvsubfhx r0,r1,r2
+ 20: 10 01 12 0e zvaddsubfhx r0,r1,r2
+ 24: 10 01 12 0f zvsubfaddhx r0,r1,r2
+ 28: 10 01 12 10 zaddwus r0,r1,r2
+ 2c: 10 01 12 11 zsubfwus r0,r1,r2
+ 30: 10 01 12 12 zaddwss r0,r1,r2
+ 34: 10 01 12 13 zsubfwss r0,r1,r2
+ 38: 10 01 12 14 zvaddhus r0,r1,r2
+ 3c: 10 01 12 15 zvsubfhus r0,r1,r2
+ 40: 10 01 12 16 zvaddhss r0,r1,r2
+ 44: 10 01 12 17 zvsubfhss r0,r1,r2
+ 48: 10 01 12 1a zvaddsubfhss r0,r1,r2
+ 4c: 10 01 12 1b zvsubfaddhss r0,r1,r2
+ 50: 10 01 12 1c zvaddhxss r0,r1,r2
+ 54: 10 01 12 1d zvsubfhxss r0,r1,r2
+ 58: 10 01 12 1e zvaddsubfhxss r0,r1,r2
+ 5c: 10 01 12 1f zvsubfaddhxss r0,r1,r2
+ 60: 10 01 12 20 zaddheuw r0,r1,r2
+ 64: 10 01 12 21 zsubfheuw r0,r1,r2
+ 68: 10 01 12 22 zaddhesw r0,r1,r2
+ 6c: 10 01 12 23 zsubfhesw r0,r1,r2
+ 70: 10 01 12 24 zaddhouw r0,r1,r2
+ 74: 10 01 12 25 zsubfhouw r0,r1,r2
+ 78: 10 01 12 26 zaddhosw r0,r1,r2
+ 7c: 10 01 12 27 zsubfhosw r0,r1,r2
+ 80: 10 01 12 2c zvmergehih r0,r1,r2
+ 84: 10 01 12 2d zvmergeloh r0,r1,r2
+ 88: 10 01 12 2e zvmergehiloh r0,r1,r2
+ 8c: 10 01 12 2f zvmergelohih r0,r1,r2
+ 90: 10 01 12 30 zvcmpgthu cr0,r1,r2
+ 94: 10 01 12 30 zvcmpgthu cr0,r1,r2
+ 98: 10 01 12 31 zvcmplthu cr0,r1,r2
+ 9c: 10 01 12 31 zvcmplthu cr0,r1,r2
+ a0: 10 01 12 32 zvcmpeqh cr0,r1,r2
+ a4: 10 01 12 38 zpkswgshfrs r0,r1,r2
+ a8: 10 01 12 39 zpkswgswfrs r0,r1,r2
+ ac: 10 01 12 3a zvpkshgwshfrs r0,r1,r2
+ b0: 10 01 12 3b zvpkswshfrs r0,r1,r2
+ b4: 10 01 12 3c zvpkswuhs r0,r1,r2
+ b8: 10 01 12 3d zvpkswshs r0,r1,r2
+ bc: 10 01 12 3e zvpkuwuhs r0,r1,r2
+ c0: 10 10 02 3f zvsplatih r0,-16
+ c4: 10 10 0a 3f zvsplatfih r0,-16
+ c8: 10 01 2a 3f zcntlsw r0,r1
+ cc: 10 01 32 3f zvcntlzh r0,r1
+ d0: 10 01 3a 3f zvcntlsh r0,r1
+ d4: 10 01 4a 3f znegws r0,r1
+ d8: 10 01 52 3f zvnegh r0,r1
+ dc: 10 01 5a 3f zvneghs r0,r1
+ e0: 10 01 62 3f zvnegho r0,r1
+ e4: 10 01 6a 3f zvneghos r0,r1
+ e8: 10 01 82 3f zrndwh r0,r1
+ ec: 10 01 8a 3f zrndwhss r0,r1
+ f0: 10 01 a2 3f zvabsh r0,r1
+ f4: 10 01 aa 3f zvabshs r0,r1
+ f8: 10 01 b2 3f zabsw r0,r1
+ fc: 10 01 ba 3f zabsws r0,r1
+ 100: 10 01 c2 3f zsatswuw r0,r1
+ 104: 10 01 ca 3f zsatuwsw r0,r1
+ 108: 10 01 d2 3f zsatswuh r0,r1
+ 10c: 10 01 da 3f zsatswsh r0,r1
+ 110: 10 01 e2 3f zvsatshuh r0,r1
+ 114: 10 01 ea 3f zvsatuhsh r0,r1
+ 118: 10 01 f2 3f zsatuwuh r0,r1
+ 11c: 10 01 fa 3f zsatuwsh r0,r1
+ 120: 10 01 12 60 zsatsduw r0,r1,r2
+ 124: 10 01 12 61 zsatsdsw r0,r1,r2
+ 128: 10 01 12 62 zsatuduw r0,r1,r2
+ 12c: 10 01 12 64 zvselh r0,r1,r2
+ 130: 10 01 12 65 zxtrw r0,r1,r2,1
+ 134: 10 01 12 68 zbrminc r0,r1,r2
+ 138: 10 01 12 69 zcircinc r0,r1,r2
+ 13c: 10 01 12 6b zdivwsf r0,r1,r2
+ 140: 10 01 12 70 zvsrhu r0,r1,r2
+ 144: 10 01 12 71 zvsrhs r0,r1,r2
+ 148: 10 01 7a 72 zvsrhiu r0,r1,15
+ 14c: 10 01 7a 73 zvsrhis r0,r1,15
+ 150: 10 01 12 74 zvslh r0,r1,r2
+ 154: 10 01 12 75 zvrlh r0,r1,r2
+ 158: 10 01 7a 76 zvslhi r0,r1,15
+ 15c: 10 01 7a 77 zvrlhi r0,r1,15
+ 160: 10 01 12 78 zvslhus r0,r1,r2
+ 164: 10 01 12 79 zvslhss r0,r1,r2
+ 168: 10 01 7a 7a zvslhius r0,r1,15
+ 16c: 10 01 7a 7b zvslhiss r0,r1,15
+ 170: 10 01 12 7c zslwus r0,r1,r2
+ 174: 10 01 12 7d zslwss r0,r1,r2
+ 178: 10 01 7a 7e zslwius r0,r1,15
+ 17c: 10 01 7a 7f zslwiss r0,r1,15
+ 180: 10 01 14 60 zaddwgui r0,r1,r2
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+ 6a0: 10 01 16 24 zmheouian r0,r1,r2
+ 6a4: 10 01 16 25 zmheouians r0,r1,r2
+ 6a8: 10 01 16 28 zmheosi r0,r1,r2
+ 6ac: 10 01 16 2a zmheosiaa r0,r1,r2
+ 6b0: 10 01 16 2b zmheosiaas r0,r1,r2
+ 6b4: 10 01 16 2c zmheosian r0,r1,r2
+ 6b8: 10 01 16 2d zmheosians r0,r1,r2
+ 6bc: 10 01 16 30 zmheosui r0,r1,r2
+ 6c0: 10 01 16 32 zmheosuiaa r0,r1,r2
+ 6c4: 10 01 16 33 zmheosuiaas r0,r1,r2
+ 6c8: 10 01 16 34 zmheosuian r0,r1,r2
+ 6cc: 10 01 16 35 zmheosuians r0,r1,r2
+ 6d0: 10 01 16 38 zmheosf r0,r1,r2
+ 6d4: 10 01 16 39 zmheosfr r0,r1,r2
+ 6d8: 10 01 16 3a zmheosfaas r0,r1,r2
+ 6dc: 10 01 16 3b zmheosfraas r0,r1,r2
+ 6e0: 10 01 16 3c zmheosfans r0,r1,r2
+ 6e4: 10 01 16 3d zmheosfrans r0,r1,r2
+ 6e8: 10 01 16 40 zmhoui r0,r1,r2
+ 6ec: 10 01 16 42 zmhouiaa r0,r1,r2
+ 6f0: 10 01 16 43 zmhouiaas r0,r1,r2
+ 6f4: 10 01 16 44 zmhouian r0,r1,r2
+ 6f8: 10 01 16 45 zmhouians r0,r1,r2
+ 6fc: 10 01 16 48 zmhosi r0,r1,r2
+ 700: 10 01 16 4a zmhosiaa r0,r1,r2
+ 704: 10 01 16 4b zmhosiaas r0,r1,r2
+ 708: 10 01 16 4c zmhosian r0,r1,r2
+ 70c: 10 01 16 4d zmhosians r0,r1,r2
+ 710: 10 01 16 50 zmhosui r0,r1,r2
+ 714: 10 01 16 52 zmhosuiaa r0,r1,r2
+ 718: 10 01 16 53 zmhosuiaas r0,r1,r2
+ 71c: 10 01 16 54 zmhosuian r0,r1,r2
+ 720: 10 01 16 55 zmhosuians r0,r1,r2
+ 724: 10 01 16 58 zmhosf r0,r1,r2
+ 728: 10 01 16 59 zmhosfr r0,r1,r2
+ 72c: 10 01 16 5a zmhosfaas r0,r1,r2
+ 730: 10 01 16 5b zmhosfraas r0,r1,r2
+ 734: 10 01 16 5c zmhosfans r0,r1,r2
+ 738: 10 01 16 5d zmhosfrans r0,r1,r2
+ 73c: 10 01 16 60 zvmhuih r0,r1,r2
+ 740: 10 01 16 61 zvmhuihs r0,r1,r2
+ 744: 10 01 16 62 zvmhuiaah r0,r1,r2
+ 748: 10 01 16 63 zvmhuiaahs r0,r1,r2
+ 74c: 10 01 16 64 zvmhuianh r0,r1,r2
+ 750: 10 01 16 65 zvmhuianhs r0,r1,r2
+ 754: 10 01 16 69 zvmhsihs r0,r1,r2
+ 758: 10 01 16 6b zvmhsiaahs r0,r1,r2
+ 75c: 10 01 16 6d zvmhsianhs r0,r1,r2
+ 760: 10 01 16 71 zvmhsuihs r0,r1,r2
+ 764: 10 01 16 73 zvmhsuiaahs r0,r1,r2
+ 768: 10 01 16 75 zvmhsuianhs r0,r1,r2
+ 76c: 10 01 16 78 zvmhsfh r0,r1,r2
+ 770: 10 01 16 79 zvmhsfrh r0,r1,r2
+ 774: 10 01 16 7a zvmhsfaahs r0,r1,r2
+ 778: 10 01 16 7b zvmhsfraahs r0,r1,r2
+ 77c: 10 01 16 7c zvmhsfanhs r0,r1,r2
+ 780: 10 01 16 7d zvmhsfranhs r0,r1,r2
+ 784: 10 01 16 80 zvdotphaui r0,r1,r2
+ 788: 10 01 16 81 zvdotphauis r0,r1,r2
+ 78c: 10 01 16 82 zvdotphauiaa r0,r1,r2
+ 790: 10 01 16 83 zvdotphauiaas r0,r1,r2
+ 794: 10 01 16 84 zvdotphauian r0,r1,r2
+ 798: 10 01 16 85 zvdotphauians r0,r1,r2
+ 79c: 10 01 16 88 zvdotphasi r0,r1,r2
+ 7a0: 10 01 16 89 zvdotphasis r0,r1,r2
+ 7a4: 10 01 16 8a zvdotphasiaa r0,r1,r2
+ 7a8: 10 01 16 8b zvdotphasiaas r0,r1,r2
+ 7ac: 10 01 16 8c zvdotphasian r0,r1,r2
+ 7b0: 10 01 16 8d zvdotphasians r0,r1,r2
+ 7b4: 10 01 16 90 zvdotphasui r0,r1,r2
+ 7b8: 10 01 16 91 zvdotphasuis r0,r1,r2
+ 7bc: 10 01 16 92 zvdotphasuiaa r0,r1,r2
+ 7c0: 10 01 16 93 zvdotphasuiaas r0,r1,r2
+ 7c4: 10 01 16 94 zvdotphasuian r0,r1,r2
+ 7c8: 10 01 16 95 zvdotphasuians r0,r1,r2
+ 7cc: 10 01 16 98 zvdotphasfs r0,r1,r2
+ 7d0: 10 01 16 99 zvdotphasfrs r0,r1,r2
+ 7d4: 10 01 16 9a zvdotphasfaas r0,r1,r2
+ 7d8: 10 01 16 9b zvdotphasfraas r0,r1,r2
+ 7dc: 10 01 16 9c zvdotphasfans r0,r1,r2
+ 7e0: 10 01 16 9d zvdotphasfrans r0,r1,r2
+ 7e4: 10 01 16 a0 zvdotphxaui r0,r1,r2
+ 7e8: 10 01 16 a1 zvdotphxauis r0,r1,r2
+ 7ec: 10 01 16 a2 zvdotphxauiaa r0,r1,r2
+ 7f0: 10 01 16 a3 zvdotphxauiaas r0,r1,r2
+ 7f4: 10 01 16 a4 zvdotphxauian r0,r1,r2
+ 7f8: 10 01 16 a5 zvdotphxauians r0,r1,r2
+ 7fc: 10 01 16 a8 zvdotphxasi r0,r1,r2
+ 800: 10 01 16 a9 zvdotphxasis r0,r1,r2
+ 804: 10 01 16 aa zvdotphxasiaa r0,r1,r2
+ 808: 10 01 16 ab zvdotphxasiaas r0,r1,r2
+ 80c: 10 01 16 ac zvdotphxasian r0,r1,r2
+ 810: 10 01 16 ad zvdotphxasians r0,r1,r2
+ 814: 10 01 16 b0 zvdotphxasui r0,r1,r2
+ 818: 10 01 16 b1 zvdotphxasuis r0,r1,r2
+ 81c: 10 01 16 b2 zvdotphxasuiaa r0,r1,r2
+ 820: 10 01 16 b3 zvdotphxasuiaas r0,r1,r2
+ 824: 10 01 16 b4 zvdotphxasuian r0,r1,r2
+ 828: 10 01 16 b5 zvdotphxasuians r0,r1,r2
+ 82c: 10 01 16 b8 zvdotphxasfs r0,r1,r2
+ 830: 10 01 16 b9 zvdotphxasfrs r0,r1,r2
+ 834: 10 01 16 ba zvdotphxasfaas r0,r1,r2
+ 838: 10 01 16 bb zvdotphxasfraas r0,r1,r2
+ 83c: 10 01 16 bc zvdotphxasfans r0,r1,r2
+ 840: 10 01 16 bd zvdotphxasfrans r0,r1,r2
+ 844: 10 01 16 c0 zvdotphsui r0,r1,r2
+ 848: 10 01 16 c1 zvdotphsuis r0,r1,r2
+ 84c: 10 01 16 c2 zvdotphsuiaa r0,r1,r2
+ 850: 10 01 16 c3 zvdotphsuiaas r0,r1,r2
+ 854: 10 01 16 c4 zvdotphsuian r0,r1,r2
+ 858: 10 01 16 c5 zvdotphsuians r0,r1,r2
+ 85c: 10 01 16 c8 zvdotphssi r0,r1,r2
+ 860: 10 01 16 c9 zvdotphssis r0,r1,r2
+ 864: 10 01 16 ca zvdotphssiaa r0,r1,r2
+ 868: 10 01 16 cb zvdotphssiaas r0,r1,r2
+ 86c: 10 01 16 cc zvdotphssian r0,r1,r2
+ 870: 10 01 16 cd zvdotphssians r0,r1,r2
+ 874: 10 01 16 d0 zvdotphssui r0,r1,r2
+ 878: 10 01 16 d1 zvdotphssuis r0,r1,r2
+ 87c: 10 01 16 d2 zvdotphssuiaa r0,r1,r2
+ 880: 10 01 16 d3 zvdotphssuiaas r0,r1,r2
+ 884: 10 01 16 d4 zvdotphssuian r0,r1,r2
+ 888: 10 01 16 d5 zvdotphssuians r0,r1,r2
+ 88c: 10 01 16 d8 zvdotphssfs r0,r1,r2
+ 890: 10 01 16 d9 zvdotphssfrs r0,r1,r2
+ 894: 10 01 16 da zvdotphssfaas r0,r1,r2
+ 898: 10 01 16 db zvdotphssfraas r0,r1,r2
+ 89c: 10 01 16 dc zvdotphssfans r0,r1,r2
+ 8a0: 10 01 16 dd zvdotphssfrans r0,r1,r2
+ 8a4: 10 01 16 e1 zmwluis r0,r1,r2
+ 8a8: 10 01 16 e2 zmwluiaa r0,r1,r2
+ 8ac: 10 01 16 e3 zmwluiaas r0,r1,r2
+ 8b0: 10 01 16 e4 zmwluian r0,r1,r2
+ 8b4: 10 01 16 e5 zmwluians r0,r1,r2
+ 8b8: 10 01 16 e9 zmwlsis r0,r1,r2
+ 8bc: 10 01 16 eb zmwlsiaas r0,r1,r2
+ 8c0: 10 01 16 ed zmwlsians r0,r1,r2
+ 8c4: 10 01 16 f1 zmwlsuis r0,r1,r2
+ 8c8: 10 01 16 f3 zmwlsuiaas r0,r1,r2
+ 8cc: 10 01 16 f5 zmwlsuians r0,r1,r2
+ 8d0: 10 01 16 f8 zmwsf r0,r1,r2
+ 8d4: 10 01 16 f9 zmwsfr r0,r1,r2
+ 8d8: 10 01 16 fa zmwsfaas r0,r1,r2
+ 8dc: 10 01 16 fb zmwsfraas r0,r1,r2
+ 8e0: 10 01 16 fc zmwsfans r0,r1,r2
+ 8e4: 10 01 16 fd zmwsfrans r0,r1,r2
+ 8e8: 10 01 13 00 zlddx r0,r1,r2
+ 8ec: 10 01 13 01 zldd r0,16\(r1\)
+ 8f0: 10 01 13 02 zldwx r0,r1,r2
+ 8f4: 10 01 13 03 zldw r0,16\(r1\)
+ 8f8: 10 01 13 04 zldhx r0,r1,r2
+ 8fc: 10 01 13 05 zldh r0,16\(r1\)
+ 900: 10 01 13 08 zlwgsfdx r0,r1,r2
+ 904: 10 01 13 09 zlwgsfd r0,8\(r1\)
+ 908: 10 01 13 0a zlwwosdx r0,r1,r2
+ 90c: 10 01 13 0b zlwwosd r0,8\(r1\)
+ 910: 10 01 13 0c zlwhsplatwdx r0,r1,r2
+ 914: 10 01 13 0d zlwhsplatwd r0,8\(r1\)
+ 918: 10 01 13 0e zlwhsplatdx r0,r1,r2
+ 91c: 10 01 13 0f zlwhsplatd r0,8\(r1\)
+ 920: 10 01 13 10 zlwhgwsfdx r0,r1,r2
+ 924: 10 01 13 11 zlwhgwsfd r0,8\(r1\)
+ 928: 10 01 13 12 zlwhedx r0,r1,r2
+ 92c: 10 01 13 13 zlwhed r0,8\(r1\)
+ 930: 10 01 13 14 zlwhosdx r0,r1,r2
+ 934: 10 01 13 15 zlwhosd r0,8\(r1\)
+ 938: 10 01 13 16 zlwhoudx r0,r1,r2
+ 93c: 10 01 13 17 zlwhoud r0,8\(r1\)
+ 940: 10 01 13 18 zlwhx r0,r1,r2
+ 944: 10 01 13 19 zlwh r0,8\(r1\)
+ 948: 10 01 13 1a zlwwx r0,r1,r2
+ 94c: 10 01 13 1b zlww r0,8\(r1\)
+ 950: 10 01 13 1c zlhgwsfx r0,r1,r2
+ 954: 10 01 13 1d zlhgwsf r0,4\(r1\)
+ 958: 10 01 13 1e zlhhsplatx r0,r1,r2
+ 95c: 10 01 13 1f zlhhsplat r0,4\(r1\)
+ 960: 10 01 13 20 zstddx r0,r1,r2
+ 964: 10 01 13 21 zstdd r0,16\(r1\)
+ 968: 10 01 13 22 zstdwx r0,r1,r2
+ 96c: 10 01 13 23 zstdw r0,16\(r1\)
+ 970: 10 01 13 24 zstdhx r0,r1,r2
+ 974: 10 01 13 25 zstdh r0,16\(r1\)
+ 978: 10 01 13 28 zstwhedx r0,r1,r2
+ 97c: 10 01 13 29 zstwhed r0,8\(r1\)
+ 980: 10 01 13 2a zstwhodx r0,r1,r2
+ 984: 10 01 13 2b zstwhod r0,8\(r1\)
+ 988: 10 01 13 30 zlhhex r0,r1,r2
+ 98c: 10 01 13 31 zlhhe r0,4\(r1\)
+ 990: 10 01 13 32 zlhhosx r0,r1,r2
+ 994: 10 01 13 33 zlhhos r0,4\(r1\)
+ 998: 10 01 13 34 zlhhoux r0,r1,r2
+ 99c: 10 01 13 35 zlhhou r0,4\(r1\)
+ 9a0: 10 01 13 38 zsthex r0,r1,r2
+ 9a4: 10 01 13 39 zsthe r0,4\(r1\)
+ 9a8: 10 01 13 3a zsthox r0,r1,r2
+ 9ac: 10 01 13 3b zstho r0,4\(r1\)
+ 9b0: 10 01 13 3c zstwhx r0,r1,r2
+ 9b4: 10 01 13 3d zstwh r0,8\(r1\)
+ 9b8: 10 01 13 3e zstwwx r0,r1,r2
+ 9bc: 10 01 13 3f zstww r0,8\(r1\)
+ 9c0: 10 01 13 40 zlddmx r0,r1,r2
+ 9c4: 10 01 13 41 zlddu r0,16\(r1\)
+ 9c8: 10 01 13 42 zldwmx r0,r1,r2
+ 9cc: 10 01 13 43 zldwu r0,16\(r1\)
+ 9d0: 10 01 13 44 zldhmx r0,r1,r2
+ 9d4: 10 01 13 45 zldhu r0,16\(r1\)
+ 9d8: 10 01 13 48 zlwgsfdmx r0,r1,r2
+ 9dc: 10 01 13 49 zlwgsfdu r0,8\(r1\)
+ 9e0: 10 01 13 4a zlwwosdmx r0,r1,r2
+ 9e4: 10 01 13 4b zlwwosdu r0,8\(r1\)
+ 9e8: 10 01 13 4c zlwhsplatwdmx r0,r1,r2
+ 9ec: 10 01 13 4d zlwhsplatwdu r0,8\(r1\)
+ 9f0: 10 01 13 4e zlwhsplatdmx r0,r1,r2
+ 9f4: 10 01 13 4f zlwhsplatdu r0,8\(r1\)
+ 9f8: 10 01 13 50 zlwhgwsfdmx r0,r1,r2
+ 9fc: 10 01 13 51 zlwhgwsfdu r0,8\(r1\)
+ a00: 10 01 13 52 zlwhedmx r0,r1,r2
+ a04: 10 01 13 53 zlwhedu r0,8\(r1\)
+ a08: 10 01 13 54 zlwhosdmx r0,r1,r2
+ a0c: 10 01 13 55 zlwhosdu r0,8\(r1\)
+ a10: 10 01 13 56 zlwhoudmx r0,r1,r2
+ a14: 10 01 13 57 zlwhoudu r0,8\(r1\)
+ a18: 10 01 13 58 zlwhmx r0,r1,r2
+ a1c: 10 01 13 59 zlwhu r0,8\(r1\)
+ a20: 10 01 13 5a zlwwmx r0,r1,r2
+ a24: 10 01 13 5b zlwwu r0,8\(r1\)
+ a28: 10 01 13 5c zlhgwsfmx r0,r1,r2
+ a2c: 10 01 13 5d zlhgwsfu r0,4\(r1\)
+ a30: 10 01 13 5e zlhhsplatmx r0,r1,r2
+ a34: 10 01 13 5f zlhhsplatu r0,4\(r1\)
+ a38: 10 01 13 60 zstddmx r0,r1,r2
+ a3c: 10 01 13 61 zstddu r0,16\(r1\)
+ a40: 10 01 13 62 zstdwmx r0,r1,r2
+ a44: 10 01 13 63 zstdwu r0,16\(r1\)
+ a48: 10 01 13 64 zstdhmx r0,r1,r2
+ a4c: 10 01 13 65 zstdhu r0,16\(r1\)
+ a50: 10 01 13 68 zstwhedmx r0,r1,r2
+ a54: 10 01 13 69 zstwhedu r0,8\(r1\)
+ a58: 10 01 13 6a zstwhodmx r0,r1,r2
+ a5c: 10 01 13 6b zstwhodu r0,8\(r1\)
+ a60: 10 01 13 70 zlhhemx r0,r1,r2
+ a64: 10 01 13 71 zlhheu r0,4\(r1\)
+ a68: 10 01 13 72 zlhhosmx r0,r1,r2
+ a6c: 10 01 13 73 zlhhosu r0,4\(r1\)
+ a70: 10 01 13 74 zlhhoumx r0,r1,r2
+ a74: 10 01 13 75 zlhhouu r0,4\(r1\)
+ a78: 10 01 13 78 zsthemx r0,r1,r2
+ a7c: 10 01 13 79 zstheu r0,4\(r1\)
+ a80: 10 01 13 7a zsthomx r0,r1,r2
+ a84: 10 01 13 7b zsthou r0,4\(r1\)
+ a88: 10 01 13 7c zstwhmx r0,r1,r2
+ a8c: 10 01 13 7d zstwhu r0,8\(r1\)
+ a90: 10 01 13 7e zstwwmx r0,r1,r2
+ a94: 10 01 13 7f zstwwu r0,8\(r1\)
\ No newline at end of file
diff --git a/gas/testsuite/gas/ppc/lsp.s b/gas/testsuite/gas/ppc/lsp.s
new file mode 100644
index 0000000..4b64e87
--- /dev/null
+++ b/gas/testsuite/gas/ppc/lsp.s
@@ -0,0 +1,694 @@
+# PA LSP instructions
+# CMPE200GCC-62
+ .section ".text"
+
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0
+ .equ rS,0
+ .equ UIMM, 15 ;#UIMM values >15 are illegal
+ .equ UIMM_2, 4
+ .equ UIMM_4, 8
+ .equ UIMM_8, 16
+ .equ SIMM, -16
+ .equ crD, 0
+ .equ offset, 1
+
+ zvaddih rD, rA, UIMM
+ zvsubifh rD, rA, UIMM
+ zvaddh rD, rA, rB
+ zvsubfh rD, rA, rB
+ zvaddsubfh rD, rA, rB
+ zvsubfaddh rD, rA, rB
+ zvaddhx rD, rA, rB
+ zvsubfhx rD, rA, rB
+ zvaddsubfhx rD, rA, rB
+ zvsubfaddhx rD, rA, rB
+ zaddwus rD, rA, rB
+ zsubfwus rD, rA, rB
+ zaddwss rD, rA, rB
+ zsubfwss rD, rA, rB
+ zvaddhus rD, rA, rB
+ zvsubfhus rD, rA, rB
+ zvaddhss rD, rA, rB
+ zvsubfhss rD, rA, rB
+ zvaddsubfhss rD, rA, rB
+ zvsubfaddhss rD, rA, rB
+ zvaddhxss rD, rA, rB
+ zvsubfhxss rD, rA, rB
+ zvaddsubfhxss rD, rA, rB
+ zvsubfaddhxss rD, rA, rB
+ zaddheuw rD, rA, rB
+ zsubfheuw rD, rA, rB
+ zaddhesw rD, rA, rB
+ zsubfhesw rD, rA, rB
+ zaddhouw rD, rA, rB
+ zsubfhouw rD, rA, rB
+ zaddhosw rD, rA, rB
+ zsubfhosw rD, rA, rB
+ zvmergehih rD, rA, rB
+ zvmergeloh rD, rA, rB
+ zvmergehiloh rD, rA, rB
+ zvmergelohih rD, rA, rB
+ zvcmpgthu crD, rA, rB
+ zvcmpgths crD, rA, rB
+ zvcmplthu crD, rA, rB
+ zvcmplths crD, rA, rB
+ zvcmpeqh crD, rA, rB
+ zpkswgshfrs rD, rA, rB
+ zpkswgswfrs rD, rA, rB
+ zvpkshgwshfrs rD, rA, rB
+ zvpkswshfrs rD, rA, rB
+ zvpkswuhs rD, rA, rB
+ zvpkswshs rD, rA, rB
+ zvpkuwuhs rD, rA, rB
+ zvsplatih rD, SIMM
+ zvsplatfih rD, SIMM
+ zcntlsw rD, rA
+ zvcntlzh rD, rA
+ zvcntlsh rD, rA
+ znegws rD, rA
+ zvnegh rD, rA
+ zvneghs rD, rA
+ zvnegho rD, rA
+ zvneghos rD, rA
+ zrndwh rD, rA
+ zrndwhss rD, rA
+ zvabsh rD, rA
+ zvabshs rD, rA
+ zabsw rD, rA
+ zabsws rD, rA
+ zsatswuw rD, rA
+ zsatuwsw rD, rA
+ zsatswuh rD, rA
+ zsatswsh rD, rA
+ zvsatshuh rD, rA
+ zvsatuhsh rD, rA
+ zsatuwuh rD, rA
+ zsatuwsh rD, rA
+ zsatsduw rD, rA, rB
+ zsatsdsw rD, rA, rB
+ zsatuduw rD, rA, rB
+ zvselh rD, rA, rB
+ zxtrw rD, rA, rB, offset
+ zbrminc rD, rA, rB
+ zcircinc rD, rA, rB
+ zdivwsf rD, rA, rB
+ zvsrhu rD, rA, rB
+ zvsrhs rD, rA, rB
+ zvsrhiu rD, rA, UIMM
+ zvsrhis rD, rA, UIMM
+ zvslh rD, rA, rB
+ zvrlh rD, rA, rB
+ zvslhi rD, rA, UIMM
+ zvrlhi rD, rA, UIMM
+ zvslhus rD, rA, rB
+ zvslhss rD, rA, rB
+ zvslhius rD, rA, UIMM
+ zvslhiss rD, rA, UIMM
+ zslwus rD, rA, rB
+ zslwss rD, rA, rB
+ zslwius rD, rA, UIMM
+ zslwiss rD, rA, UIMM
+ zaddwgui rD, rA, rB
+ zsubfwgui rD, rA, rB
+ zaddd rD, rA, rB
+ zsubfd rD, rA, rB
+ zvaddsubfw rD, rA, rB
+ zvsubfaddw rD, rA, rB
+ zvaddw rD, rA, rB
+ zvsubfw rD, rA, rB
+ zaddwgsi rD, rA, rB
+ zsubfwgsi rD, rA, rB
+ zadddss rD, rA, rB
+ zsubfdss rD, rA, rB
+ zvaddsubfwss rD, rA, rB
+ zvsubfaddwss rD, rA, rB
+ zvaddwss rD, rA, rB
+ zvsubfwss rD, rA, rB
+ zaddwgsf rD, rA, rB
+ zsubfwgsf rD, rA, rB
+ zadddus rD, rA, rB
+ zsubfdus rD, rA, rB
+ zvaddwus rD, rA, rB
+ zvsubfwus rD, rA, rB
+ zvunpkhgwsf rD, rA
+ zvunpkhsf rD, rA
+ zvunpkhui rD, rA
+ zvunpkhsi rD, rA
+ zunpkwgsf rD, rA
+ zvdotphgwasmf rD, rA, rB
+ zvdotphgwasmfr rD, rA, rB
+ zvdotphgwasmfaa rD, rA, rB
+ zvdotphgwasmfraa rD, rA, rB
+ zvdotphgwasmfan rD, rA, rB
+ zvdotphgwasmfran rD, rA, rB
+ zvmhulgwsmf rD, rA, rB
+ zvmhulgwsmfr rD, rA, rB
+ zvmhulgwsmfaa rD, rA, rB
+ zvmhulgwsmfraa rD, rA, rB
+ zvmhulgwsmfan rD, rA, rB
+ zvmhulgwsmfran rD, rA, rB
+ zvmhulgwsmfanp rD, rA, rB
+ zvmhulgwsmfranp rD, rA, rB
+ zmhegwsmf rD, rA, rB
+ zmhegwsmfr rD, rA, rB
+ zmhegwsmfaa rD, rA, rB
+ zmhegwsmfraa rD, rA, rB
+ zmhegwsmfan rD, rA, rB
+ zmhegwsmfran rD, rA, rB
+ zvdotphxgwasmf rD, rA, rB
+ zvdotphxgwasmfr rD, rA, rB
+ zvdotphxgwasmfaa rD, rA, rB
+ zvdotphxgwasmfraa rD, rA, rB
+ zvdotphxgwasmfan rD, rA, rB
+ zvdotphxgwasmfran rD, rA, rB
+ zvmhllgwsmf rD, rA, rB
+ zvmhllgwsmfr rD, rA, rB
+ zvmhllgwsmfaa rD, rA, rB
+ zvmhllgwsmfraa rD, rA, rB
+ zvmhllgwsmfan rD, rA, rB
+ zvmhllgwsmfran rD, rA, rB
+ zvmhllgwsmfanp rD, rA, rB
+ zvmhllgwsmfranp rD, rA, rB
+ zmheogwsmf rD, rA, rB
+ zmheogwsmfr rD, rA, rB
+ zmheogwsmfaa rD, rA, rB
+ zmheogwsmfraa rD, rA, rB
+ zmheogwsmfan rD, rA, rB
+ zmheogwsmfran rD, rA, rB
+ zvdotphgwssmf rD, rA, rB
+ zvdotphgwssmfr rD, rA, rB
+ zvdotphgwssmfaa rD, rA, rB
+ zvdotphgwssmfraa rD, rA, rB
+ zvdotphgwssmfan rD, rA, rB
+ zvdotphgwssmfran rD, rA, rB
+ zvmhuugwsmf rD, rA, rB
+ zvmhuugwsmfr rD, rA, rB
+ zvmhuugwsmfaa rD, rA, rB
+ zvmhuugwsmfraa rD, rA, rB
+ zvmhuugwsmfan rD, rA, rB
+ zvmhuugwsmfran rD, rA, rB
+ zvmhuugwsmfanp rD, rA, rB
+ zvmhuugwsmfranp rD, rA, rB
+ zmhogwsmf rD, rA, rB
+ zmhogwsmfr rD, rA, rB
+ zmhogwsmfaa rD, rA, rB
+ zmhogwsmfraa rD, rA, rB
+ zmhogwsmfan rD, rA, rB
+ zmhogwsmfran rD, rA, rB
+ zvmhxlgwsmf rD, rA, rB
+ zvmhxlgwsmfr rD, rA, rB
+ zvmhxlgwsmfaa rD, rA, rB
+ zvmhxlgwsmfraa rD, rA, rB
+ zvmhxlgwsmfan rD, rA, rB
+ zvmhxlgwsmfran rD, rA, rB
+ zvmhxlgwsmfanp rD, rA, rB
+ zvmhxlgwsmfranp rD, rA, rB
+ zmhegui rD, rA, rB
+ zvdotphgaui rD, rA, rB
+ zmheguiaa rD, rA, rB
+ zvdotphgauiaa rD, rA, rB
+ zmheguian rD, rA, rB
+ zvdotphgauian rD, rA, rB
+ zmhegsi rD, rA, rB
+ zvdotphgasi rD, rA, rB
+ zmhegsiaa rD, rA, rB
+ zvdotphgasiaa rD, rA, rB
+ zmhegsian rD, rA, rB
+ zvdotphgasian rD, rA, rB
+ zmhegsui rD, rA, rB
+ zvdotphgasui rD, rA, rB
+ zmhegsuiaa rD, rA, rB
+ zvdotphgasuiaa rD, rA, rB
+ zmhegsuian rD, rA, rB
+ zvdotphgasuian rD, rA, rB
+ zmhegsmf rD, rA, rB
+ zvdotphgasmf rD, rA, rB
+ zmhegsmfaa rD, rA, rB
+ zvdotphgasmfaa rD, rA, rB
+ zmhegsmfan rD, rA, rB
+ zvdotphgasmfan rD, rA, rB
+ zmheogui rD, rA, rB
+ zvdotphxgaui rD, rA, rB
+ zmheoguiaa rD, rA, rB
+ zvdotphxgauiaa rD, rA, rB
+ zmheoguian rD, rA, rB
+ zvdotphxgauian rD, rA, rB
+ zmheogsi rD, rA, rB
+ zvdotphxgasi rD, rA, rB
+ zmheogsiaa rD, rA, rB
+ zvdotphxgasiaa rD, rA, rB
+ zmheogsian rD, rA, rB
+ zvdotphxgasian rD, rA, rB
+ zmheogsui rD, rA, rB
+ zvdotphxgasui rD, rA, rB
+ zmheogsuiaa rD, rA, rB
+ zvdotphxgasuiaa rD, rA, rB
+ zmheogsuian rD, rA, rB
+ zvdotphxgasuian rD, rA, rB
+ zmheogsmf rD, rA, rB
+ zvdotphxgasmf rD, rA, rB
+ zmheogsmfaa rD, rA, rB
+ zvdotphxgasmfaa rD, rA, rB
+ zmheogsmfan rD, rA, rB
+ zvdotphxgasmfan rD, rA, rB
+ zmhogui rD, rA, rB
+ zvdotphgsui rD, rA, rB
+ zmhoguiaa rD, rA, rB
+ zvdotphgsuiaa rD, rA, rB
+ zmhoguian rD, rA, rB
+ zvdotphgsuian rD, rA, rB
+ zmhogsi rD, rA, rB
+ zvdotphgssi rD, rA, rB
+ zmhogsiaa rD, rA, rB
+ zvdotphgssiaa rD, rA, rB
+ zmhogsian rD, rA, rB
+ zvdotphgssian rD, rA, rB
+ zmhogsui rD, rA, rB
+ zvdotphgssui rD, rA, rB
+ zmhogsuiaa rD, rA, rB
+ zvdotphgssuiaa rD, rA, rB
+ zmhogsuian rD, rA, rB
+ zvdotphgssuian rD, rA, rB
+ zmhogsmf rD, rA, rB
+ zvdotphgssmf rD, rA, rB
+ zmhogsmfaa rD, rA, rB
+ zvdotphgssmfaa rD, rA, rB
+ zmhogsmfan rD, rA, rB
+ zvdotphgssmfan rD, rA, rB
+ zmwgui rD, rA, rB
+ zmwguiaa rD, rA, rB
+ zmwguiaas rD, rA, rB
+ zmwguian rD, rA, rB
+ zmwguians rD, rA, rB
+ zmwgsi rD, rA, rB
+ zmwgsiaa rD, rA, rB
+ zmwgsiaas rD, rA, rB
+ zmwgsian rD, rA, rB
+ zmwgsians rD, rA, rB
+ zmwgsui rD, rA, rB
+ zmwgsuiaa rD, rA, rB
+ zmwgsuiaas rD, rA, rB
+ zmwgsuian rD, rA, rB
+ zmwgsuians rD, rA, rB
+ zmwgsmf rD, rA, rB
+ zmwgsmfr rD, rA, rB
+ zmwgsmfaa rD, rA, rB
+ zmwgsmfraa rD, rA, rB
+ zmwgsmfan rD, rA, rB
+ zmwgsmfran rD, rA, rB
+ zvmhului rD, rA, rB
+ zvmhuluiaa rD, rA, rB
+ zvmhuluiaas rD, rA, rB
+ zvmhuluian rD, rA, rB
+ zvmhuluians rD, rA, rB
+ zvmhuluianp rD, rA, rB
+ zvmhuluianps rD, rA, rB
+ zvmhulsi rD, rA, rB
+ zvmhulsiaa rD, rA, rB
+ zvmhulsiaas rD, rA, rB
+ zvmhulsian rD, rA, rB
+ zvmhulsians rD, rA, rB
+ zvmhulsianp rD, rA, rB
+ zvmhulsianps rD, rA, rB
+ zvmhulsui rD, rA, rB
+ zvmhulsuiaa rD, rA, rB
+ zvmhulsuiaas rD, rA, rB
+ zvmhulsuian rD, rA, rB
+ zvmhulsuians rD, rA, rB
+ zvmhulsuianp rD, rA, rB
+ zvmhulsuianps rD, rA, rB
+ zvmhulsf rD, rA, rB
+ zvmhulsfr rD, rA, rB
+ zvmhulsfaas rD, rA, rB
+ zvmhulsfraas rD, rA, rB
+ zvmhulsfans rD, rA, rB
+ zvmhulsfrans rD, rA, rB
+ zvmhulsfanps rD, rA, rB
+ zvmhulsfranps rD, rA, rB
+ zvmhllui rD, rA, rB
+ zvmhlluiaa rD, rA, rB
+ zvmhlluiaas rD, rA, rB
+ zvmhlluian rD, rA, rB
+ zvmhlluians rD, rA, rB
+ zvmhlluianp rD, rA, rB
+ zvmhlluianps rD, rA, rB
+ zvmhllsi rD, rA, rB
+ zvmhllsiaa rD, rA, rB
+ zvmhllsiaas rD, rA, rB
+ zvmhllsian rD, rA, rB
+ zvmhllsians rD, rA, rB
+ zvmhllsianp rD, rA, rB
+ zvmhllsianps rD, rA, rB
+ zvmhllsui rD, rA, rB
+ zvmhllsuiaa rD, rA, rB
+ zvmhllsuiaas rD, rA, rB
+ zvmhllsuian rD, rA, rB
+ zvmhllsuians rD, rA, rB
+ zvmhllsuianp rD, rA, rB
+ zvmhllsuianps rD, rA, rB
+ zvmhllsf rD, rA, rB
+ zvmhllsfr rD, rA, rB
+ zvmhllsfaas rD, rA, rB
+ zvmhllsfraas rD, rA, rB
+ zvmhllsfans rD, rA, rB
+ zvmhllsfrans rD, rA, rB
+ zvmhllsfanps rD, rA, rB
+ zvmhllsfranps rD, rA, rB
+ zvmhuuui rD, rA, rB
+ zvmhuuuiaa rD, rA, rB
+ zvmhuuuiaas rD, rA, rB
+ zvmhuuuian rD, rA, rB
+ zvmhuuuians rD, rA, rB
+ zvmhuuuianp rD, rA, rB
+ zvmhuuuianps rD, rA, rB
+ zvmhuusi rD, rA, rB
+ zvmhuusiaa rD, rA, rB
+ zvmhuusiaas rD, rA, rB
+ zvmhuusian rD, rA, rB
+ zvmhuusians rD, rA, rB
+ zvmhuusianp rD, rA, rB
+ zvmhuusianps rD, rA, rB
+ zvmhuusui rD, rA, rB
+ zvmhuusuiaa rD, rA, rB
+ zvmhuusuiaas rD, rA, rB
+ zvmhuusuian rD, rA, rB
+ zvmhuusuians rD, rA, rB
+ zvmhuusuianp rD, rA, rB
+ zvmhuusuianps rD, rA, rB
+ zvmhuusf rD, rA, rB
+ zvmhuusfr rD, rA, rB
+ zvmhuusfaas rD, rA, rB
+ zvmhuusfraas rD, rA, rB
+ zvmhuusfans rD, rA, rB
+ zvmhuusfrans rD, rA, rB
+ zvmhuusfanps rD, rA, rB
+ zvmhuusfranps rD, rA, rB
+ zvmhxlui rD, rA, rB
+ zvmhxluiaa rD, rA, rB
+ zvmhxluiaas rD, rA, rB
+ zvmhxluian rD, rA, rB
+ zvmhxluians rD, rA, rB
+ zvmhxluianp rD, rA, rB
+ zvmhxluianps rD, rA, rB
+ zvmhxlsi rD, rA, rB
+ zvmhxlsiaa rD, rA, rB
+ zvmhxlsiaas rD, rA, rB
+ zvmhxlsian rD, rA, rB
+ zvmhxlsians rD, rA, rB
+ zvmhxlsianp rD, rA, rB
+ zvmhxlsianps rD, rA, rB
+ zvmhxlsui rD, rA, rB
+ zvmhxlsuiaa rD, rA, rB
+ zvmhxlsuiaas rD, rA, rB
+ zvmhxlsuian rD, rA, rB
+ zvmhxlsuians rD, rA, rB
+ zvmhxlsuianp rD, rA, rB
+ zvmhxlsuianps rD, rA, rB
+ zvmhxlsf rD, rA, rB
+ zvmhxlsfr rD, rA, rB
+ zvmhxlsfaas rD, rA, rB
+ zvmhxlsfraas rD, rA, rB
+ zvmhxlsfans rD, rA, rB
+ zvmhxlsfrans rD, rA, rB
+ zvmhxlsfanps rD, rA, rB
+ zvmhxlsfranps rD, rA, rB
+ zmheui rD, rA, rB
+ zmheuiaa rD, rA, rB
+ zmheuiaas rD, rA, rB
+ zmheuian rD, rA, rB
+ zmheuians rD, rA, rB
+ zmhesi rD, rA, rB
+ zmhesiaa rD, rA, rB
+ zmhesiaas rD, rA, rB
+ zmhesian rD, rA, rB
+ zmhesians rD, rA, rB
+ zmhesui rD, rA, rB
+ zmhesuiaa rD, rA, rB
+ zmhesuiaas rD, rA, rB
+ zmhesuian rD, rA, rB
+ zmhesuians rD, rA, rB
+ zmhesf rD, rA, rB
+ zmhesfr rD, rA, rB
+ zmhesfaas rD, rA, rB
+ zmhesfraas rD, rA, rB
+ zmhesfans rD, rA, rB
+ zmhesfrans rD, rA, rB
+ zmheoui rD, rA, rB
+ zmheouiaa rD, rA, rB
+ zmheouiaas rD, rA, rB
+ zmheouian rD, rA, rB
+ zmheouians rD, rA, rB
+ zmheosi rD, rA, rB
+ zmheosiaa rD, rA, rB
+ zmheosiaas rD, rA, rB
+ zmheosian rD, rA, rB
+ zmheosians rD, rA, rB
+ zmheosui rD, rA, rB
+ zmheosuiaa rD, rA, rB
+ zmheosuiaas rD, rA, rB
+ zmheosuian rD, rA, rB
+ zmheosuians rD, rA, rB
+ zmheosf rD, rA, rB
+ zmheosfr rD, rA, rB
+ zmheosfaas rD, rA, rB
+ zmheosfraas rD, rA, rB
+ zmheosfans rD, rA, rB
+ zmheosfrans rD, rA, rB
+ zmhoui rD, rA, rB
+ zmhouiaa rD, rA, rB
+ zmhouiaas rD, rA, rB
+ zmhouian rD, rA, rB
+ zmhouians rD, rA, rB
+ zmhosi rD, rA, rB
+ zmhosiaa rD, rA, rB
+ zmhosiaas rD, rA, rB
+ zmhosian rD, rA, rB
+ zmhosians rD, rA, rB
+ zmhosui rD, rA, rB
+ zmhosuiaa rD, rA, rB
+ zmhosuiaas rD, rA, rB
+ zmhosuian rD, rA, rB
+ zmhosuians rD, rA, rB
+ zmhosf rD, rA, rB
+ zmhosfr rD, rA, rB
+ zmhosfaas rD, rA, rB
+ zmhosfraas rD, rA, rB
+ zmhosfans rD, rA, rB
+ zmhosfrans rD, rA, rB
+ zvmhuih rD, rA, rB
+ zvmhuihs rD, rA, rB
+ zvmhuiaah rD, rA, rB
+ zvmhuiaahs rD, rA, rB
+ zvmhuianh rD, rA, rB
+ zvmhuianhs rD, rA, rB
+ zvmhsihs rD, rA, rB
+ zvmhsiaahs rD, rA, rB
+ zvmhsianhs rD, rA, rB
+ zvmhsuihs rD, rA, rB
+ zvmhsuiaahs rD, rA, rB
+ zvmhsuianhs rD, rA, rB
+ zvmhsfh rD, rA, rB
+ zvmhsfrh rD, rA, rB
+ zvmhsfaahs rD, rA, rB
+ zvmhsfraahs rD, rA, rB
+ zvmhsfanhs rD, rA, rB
+ zvmhsfranhs rD, rA, rB
+ zvdotphaui rD, rA, rB
+ zvdotphauis rD, rA, rB
+ zvdotphauiaa rD, rA, rB
+ zvdotphauiaas rD, rA, rB
+ zvdotphauian rD, rA, rB
+ zvdotphauians rD, rA, rB
+ zvdotphasi rD, rA, rB
+ zvdotphasis rD, rA, rB
+ zvdotphasiaa rD, rA, rB
+ zvdotphasiaas rD, rA, rB
+ zvdotphasian rD, rA, rB
+ zvdotphasians rD, rA, rB
+ zvdotphasui rD, rA, rB
+ zvdotphasuis rD, rA, rB
+ zvdotphasuiaa rD, rA, rB
+ zvdotphasuiaas rD, rA, rB
+ zvdotphasuian rD, rA, rB
+ zvdotphasuians rD, rA, rB
+ zvdotphasfs rD, rA, rB
+ zvdotphasfrs rD, rA, rB
+ zvdotphasfaas rD, rA, rB
+ zvdotphasfraas rD, rA, rB
+ zvdotphasfans rD, rA, rB
+ zvdotphasfrans rD, rA, rB
+ zvdotphxaui rD, rA, rB
+ zvdotphxauis rD, rA, rB
+ zvdotphxauiaa rD, rA, rB
+ zvdotphxauiaas rD, rA, rB
+ zvdotphxauian rD, rA, rB
+ zvdotphxauians rD, rA, rB
+ zvdotphxasi rD, rA, rB
+ zvdotphxasis rD, rA, rB
+ zvdotphxasiaa rD, rA, rB
+ zvdotphxasiaas rD, rA, rB
+ zvdotphxasian rD, rA, rB
+ zvdotphxasians rD, rA, rB
+ zvdotphxasui rD, rA, rB
+ zvdotphxasuis rD, rA, rB
+ zvdotphxasuiaa rD, rA, rB
+ zvdotphxasuiaas rD, rA, rB
+ zvdotphxasuian rD, rA, rB
+ zvdotphxasuians rD, rA, rB
+ zvdotphxasfs rD, rA, rB
+ zvdotphxasfrs rD, rA, rB
+ zvdotphxasfaas rD, rA, rB
+ zvdotphxasfraas rD, rA, rB
+ zvdotphxasfans rD, rA, rB
+ zvdotphxasfrans rD, rA, rB
+ zvdotphsui rD, rA, rB
+ zvdotphsuis rD, rA, rB
+ zvdotphsuiaa rD, rA, rB
+ zvdotphsuiaas rD, rA, rB
+ zvdotphsuian rD, rA, rB
+ zvdotphsuians rD, rA, rB
+ zvdotphssi rD, rA, rB
+ zvdotphssis rD, rA, rB
+ zvdotphssiaa rD, rA, rB
+ zvdotphssiaas rD, rA, rB
+ zvdotphssian rD, rA, rB
+ zvdotphssians rD, rA, rB
+ zvdotphssui rD, rA, rB
+ zvdotphssuis rD, rA, rB
+ zvdotphssuiaa rD, rA, rB
+ zvdotphssuiaas rD, rA, rB
+ zvdotphssuian rD, rA, rB
+ zvdotphssuians rD, rA, rB
+ zvdotphssfs rD, rA, rB
+ zvdotphssfrs rD, rA, rB
+ zvdotphssfaas rD, rA, rB
+ zvdotphssfraas rD, rA, rB
+ zvdotphssfans rD, rA, rB
+ zvdotphssfrans rD, rA, rB
+ zmwluis rD, rA, rB
+ zmwluiaa rD, rA, rB
+ zmwluiaas rD, rA, rB
+ zmwluian rD, rA, rB
+ zmwluians rD, rA, rB
+ zmwlsis rD, rA, rB
+ zmwlsiaas rD, rA, rB
+ zmwlsians rD, rA, rB
+ zmwlsuis rD, rA, rB
+ zmwlsuiaas rD, rA, rB
+ zmwlsuians rD, rA, rB
+ zmwsf rD, rA, rB
+ zmwsfr rD, rA, rB
+ zmwsfaas rD, rA, rB
+ zmwsfraas rD, rA, rB
+ zmwsfans rD, rA, rB
+ zmwsfrans rD, rA, rB
+ zlddx rD, rA, rB
+ zldd rD, UIMM_8(rA)
+ zldwx rD, rA, rB
+ zldw rD, UIMM_8(rA)
+ zldhx rD, rA, rB
+ zldh rD, UIMM_8(rA)
+ zlwgsfdx rD, rA, rB
+ zlwgsfd rD, UIMM_4(rA)
+ zlwwosdx rD, rA, rB
+ zlwwosd rD, UIMM_4(rA)
+ zlwhsplatwdx rD, rA, rB
+ zlwhsplatwd rD, UIMM_4(rA)
+ zlwhsplatdx rD, rA, rB
+ zlwhsplatd rD, UIMM_4(rA)
+ zlwhgwsfdx rD, rA, rB
+ zlwhgwsfd rD, UIMM_4(rA)
+ zlwhedx rD, rA, rB
+ zlwhed rD, UIMM_4(rA)
+ zlwhosdx rD, rA, rB
+ zlwhosd rD, UIMM_4(rA)
+ zlwhoudx rD, rA, rB
+ zlwhoud rD, UIMM_4(rA)
+ zlwhx rD, rA, rB
+ zlwh rD, UIMM_4(rA)
+ zlwwx rD, rA, rB
+ zlww rD, UIMM_4(rA)
+ zlhgwsfx rD, rA, rB
+ zlhgwsf rD, UIMM_2(rA)
+ zlhhsplatx rD, rA, rB
+ zlhhsplat rD, UIMM_2(rA)
+ zstddx rS, rA, rB
+ zstdd rS, UIMM_8(rA)
+ zstdwx rS, rA, rB
+ zstdw rS, UIMM_8(rA)
+ zstdhx rS, rA, rB
+ zstdh rS, UIMM_8(rA)
+ zstwhedx rS, rA, rB
+ zstwhed rS, UIMM_4(rA)
+ zstwhodx rS, rA, rB
+ zstwhod rS, UIMM_4(rA)
+ zlhhex rS, rA, rB
+ zlhhe rD, UIMM_2(rA)
+ zlhhosx rS, rA, rB
+ zlhhos rD, UIMM_2(rA)
+ zlhhoux rS, rA, rB
+ zlhhou rD, UIMM_2(rA)
+ zsthex rS, rA, rB
+ zsthe rS, UIMM_2(rA)
+ zsthox rS, rA, rB
+ zstho rS, UIMM_2(rA)
+ zstwhx rS, rA, rB
+ zstwh rS, UIMM_4(rA)
+ zstwwx rS, rA, rB
+ zstww rS, UIMM_4(rA)
+ zlddmx rD, rA, rB
+ zlddu rD, UIMM_8(rA)
+ zldwmx rD, rA, rB
+ zldwu rD, UIMM_8(rA)
+ zldhmx rD, rA, rB
+ zldhu rD, UIMM_8(rA)
+ zlwgsfdmx rD, rA, rB
+ zlwgsfdu rD, UIMM_4(rA)
+ zlwwosdmx rD, rA, rB
+ zlwwosdu rD, UIMM_4(rA)
+ zlwhsplatwdmx rD, rA, rB
+ zlwhsplatwdu rD, UIMM_4(rA)
+ zlwhsplatdmx rD, rA, rB
+ zlwhsplatdu rD, UIMM_4(rA)
+ zlwhgwsfdmx rD, rA, rB
+ zlwhgwsfdu rD, UIMM_4(rA)
+ zlwhedmx rD, rA, rB
+ zlwhedu rD, UIMM_4(rA)
+ zlwhosdmx rD, rA, rB
+ zlwhosdu rD, UIMM_4(rA)
+ zlwhoudmx rD, rA, rB
+ zlwhoudu rD, UIMM_4(rA)
+ zlwhmx rD, rA, rB
+ zlwhu rD, UIMM_4(rA)
+ zlwwmx rD, rA, rB
+ zlwwu rD, UIMM_4(rA)
+ zlhgwsfmx rD, rA, rB
+ zlhgwsfu rD, UIMM_2(rA)
+ zlhhsplatmx rD, rA, rB
+ zlhhsplatu rD, UIMM_2(rA)
+ zstddmx rS, rA, rB
+ zstddu rS, UIMM_8(rA)
+ zstdwmx rS, rA, rB
+ zstdwu rS, UIMM_8(rA)
+ zstdhmx rS, rA, rB
+ zstdhu rS, UIMM_8(rA)
+ zstwhedmx rS, rA, rB
+ zstwhedu rS, UIMM_4(rA)
+ zstwhodmx rD, rA, rB
+ zstwhodu rS, UIMM_4(rA)
+ zlhhemx rD, rA, rB
+ zlhheu rD, UIMM_2(rA)
+ zlhhosmx rD, rA, rB
+ zlhhosu rD, UIMM_2(rA)
+ zlhhoumx rD, rA, rB
+ zlhhouu rD, UIMM_2(rA)
+ zsthemx rS, rA, rB
+ zstheu rS, UIMM_2(rA)
+ zsthomx rS, rA, rB
+ zsthou rS, UIMM_2(rA)
+ zstwhmx rS, rA, rB
+ zstwhu rS, UIMM_4(rA)
+ zstwwmx rS, rA, rB
+ zstwwu rS, UIMM_4(rA)
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 55367ad..bbe64be 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -60,6 +60,11 @@ if { [istarget powerpc*-*-*] } then {
run_dump_test "vle-simple-4"
run_dump_test "vle-simple-5"
run_dump_test "vle-simple-6"
+
+ #fail expected until get_powerpc_dialect() patch not applied
+ setup_xfail "*-*-*"
+ run_dump_test "lsp"
+ run_dump_test "lsp-checks"
}
}
diff --git a/include/ChangeLog b/include/ChangeLog
index fcf8466..4e3f59f 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2017-08-19 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com>
+
+ * opcode/ppc.h (PPC_OPCODE_LSP): New define.
+
2017-08-14 Gustavo Romero <gromero@linux.vnet.ibm.com>
* elf/common.h (NT_PPC_TAR): New macro.
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index cec0e10..a87fb02 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -215,6 +215,9 @@ extern const int vle_num_opcodes;
the underlying machine instruction. */
#define PPC_OPCODE_RAW 0x40000000000ull
+/* Opcode is supported by PowerPC LSP */
+#define PPC_OPCODE_LSP 0x80000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5cbe7e0..9c0ed6b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,38 @@
+2017-08-19 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com>
+
+ * ppc-opc.c (): Add LSP opcodes
+ (insert_evuimm2_ex0): New function
+ (extract_evuimm2_ex0: Likewise.
+ (insert_evuimm4_ex0): Likewise.
+ (extract_evuimm4_ex0): Likewise.
+ (insert_evuimm8_ex0): Likewise.
+ (extract_evuimm8_ex0): Likewise.
+ (insert_evuimm_lt16): Likewise.
+ (extract_evuimm_lt16): Likewise.
+ (insert_rD_rS_even): Likewise.
+ (extract_rD_rS_even): Likewise.
+ (insert_off_lsp): Likewise.
+ (extract_off_lsp): Likewise.
+ (RD_EVEN): New operand.
+ (RS_EVEN): Likewise.
+ (RSQ): Adjust
+ (EVUIMM_LT16): New operand.
+ (HTM_SI): Adjust
+ (EVUIMM_2_EX0): New operand.
+ (EVUIMM_4): Adjust
+ (EVUIMM_4_EX0): New operand.
+ (EVUIMM_8): Adjust
+ (EVUIMM_8_EX0): New operand.
+ (WS): Adjust
+ (VX_OFF): New operand.
+ (VX_LSP): New macro.
+ (VX_LSP_MASK): Likewise.
+ (VX_LSP_OFF_MASK): Likewise.
+ (PPC_OPCODE_LSP): Likewise.
+ (vle_opcodes): Add LSP opcodes.
+ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle"
+
2017-08-09 Jiong Wang <jiong.wang@arm.com>
* arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 5e89c50..d75e59d 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -233,7 +233,7 @@ struct ppc_mopt ppc_opts[] = {
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
- | PPC_OPCODE_E500),
+ | PPC_OPCODE_E500 | PPC_OPCODE_LSP),
PPC_OPCODE_VLE },
{ "vsx", PPC_OPCODE_PPC,
PPC_OPCODE_VSX },
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 426261a..12eb1af 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -131,6 +131,18 @@ static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **
static long extract_vleui (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
static long extract_vleil (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_evuimm2_ex0 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_evuimm2_ex0 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_evuimm4_ex0 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_evuimm4_ex0 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_evuimm8_ex0 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_evuimm8_ex0 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_evuimm_lt16 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_evuimm_lt16 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_rD_rS_even (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_rD_rS_even (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_off_lsp (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_off_lsp (unsigned long, ppc_cpu_t, int *);
/* The operands table.
@@ -583,9 +595,13 @@ const struct powerpc_operand powerpc_operands[] =
#define RD RS
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
+#define RD_EVEN RS + 1
+#define RS_EVEN RD_EVEN
+ { 0x1f, 21, insert_rD_rS_even, extract_rD_rS_even, PPC_OPERAND_GPR },
+
/* The RS and RT fields of the DS form stq and DQ form lq instructions,
which have special value restrictions. */
-#define RSQ RS + 1
+#define RSQ RS_EVEN + 1
#define RTQ RSQ
#define Q_MASK (1 << 21)
{ 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
@@ -643,8 +659,11 @@ const struct powerpc_operand powerpc_operands[] =
#define FC SH
{ 0x1f, 11, NULL, NULL, 0 },
+#define EVUIMM_LT16 SH + 1
+ { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 },
+
/* The SI field in a HTM X form instruction. */
-#define HTM_SI SH + 1
+#define HTM_SI EVUIMM_LT16 + 1
{ 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
/* The SH field in an MD form instruction. This is split. */
@@ -794,16 +813,25 @@ const struct powerpc_operand powerpc_operands[] =
#define EVUIMM_2 SHB + 1
{ 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
+#define EVUIMM_2_EX0 EVUIMM_2 + 1
+ { 0x3e, 10, insert_evuimm2_ex0, extract_evuimm2_ex0, PPC_OPERAND_PARENS },
+
/* The other UIMM field in a word EVX form instruction. */
-#define EVUIMM_4 EVUIMM_2 + 1
+#define EVUIMM_4 EVUIMM_2_EX0 + 1
{ 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
+#define EVUIMM_4_EX0 EVUIMM_4 + 1
+ { 0x7c, 9, insert_evuimm4_ex0, extract_evuimm4_ex0, PPC_OPERAND_PARENS },
+
/* The other UIMM field in a double EVX form instruction. */
-#define EVUIMM_8 EVUIMM_4 + 1
+#define EVUIMM_8 EVUIMM_4_EX0 + 1
{ 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
+#define EVUIMM_8_EX0 EVUIMM_8 + 1
+ { 0xf8, 8, insert_evuimm8_ex0, extract_evuimm8_ex0, PPC_OPERAND_PARENS },
+
/* The WS or DRM field in an X form instruction. */
-#define WS EVUIMM_8 + 1
+#define WS EVUIMM_8_EX0 + 1
#define DRM WS
{ 0x7, 11, NULL, NULL, 0 },
@@ -970,6 +998,9 @@ const struct powerpc_operand powerpc_operands[] =
/* The 8-bit IMM8 field in a XX1 form instruction. */
#define IMM8 IH + 1
{ 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
+
+#define VX_OFF IMM8 + 1
+ { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -2411,6 +2442,167 @@ extract_vleil (unsigned long insn,
return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
}
+static unsigned long
+insert_evuimm2_ex0 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value > 0 && value <= 0x3e)
+ return insn | ((value & 0x3e) << 10);
+ else
+ {
+ *errmsg = _("UIMM = 00000 is illegal");
+ return 0;
+ }
+}
+
+static long
+extract_evuimm2_ex0 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ long value = ((insn >> 10) & 0x3e);
+ if (value == 0)
+ *invalid = 1;
+
+ return value;
+}
+
+static unsigned long
+insert_evuimm4_ex0 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value > 0 && value <= 0x7c)
+ return insn | ((value & 0x7c) << 9);
+ else
+ {
+ *errmsg = _("UIMM = 00000 is illegal");
+ return 0;
+ }
+}
+
+static long
+extract_evuimm4_ex0 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ long value = ((insn >> 9) & 0x7c);
+ if (value == 0)
+ *invalid = 1;
+
+ return value;
+}
+
+static unsigned long
+insert_evuimm8_ex0 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value > 0 && value <= 0xf8)
+ return insn | ((value & 0xf8) << 8);
+ else
+ {
+ *errmsg = _("UIMM = 00000 is illegal");
+ return 0;
+ }
+}
+
+static long
+extract_evuimm8_ex0 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ long value = ((insn >> 8) & 0xf8);
+ if (value == 0)
+ *invalid = 1;
+
+ return value;
+}
+
+static unsigned long
+insert_evuimm_lt16 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value >= 0 && value <= 15)
+ return insn | ((value & 0xf) << 11);
+ else
+ {
+ *errmsg = _("UIMM values >15 are illegal");
+ return 0;
+ }
+}
+
+static long
+extract_evuimm_lt16 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ long value = ((insn >> 11) & 0x1f);
+ if (value > 15)
+ *invalid = 1;
+
+ return value;
+}
+
+static unsigned long
+insert_rD_rS_even (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if ((value & 0x1) == 0)
+ return insn | ((value & 0x1e) << 21);
+ else
+ {
+ *errmsg = _("GPR odd is illegal");
+ return 0;
+ }
+}
+
+static long
+extract_rD_rS_even (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ long value = ((insn >> 21) & 0x1f);
+ if ((value & 0x1) != 0)
+ *invalid = 1;
+
+ return value;
+}
+
+static unsigned long
+insert_off_lsp (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value > 0 && value <= 0x3)
+ return insn | (value & 0x3);
+ else
+ {
+ *errmsg = _("invalid offset");
+ return 0;
+ }
+}
+
+static long
+extract_off_lsp (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ long value = (insn & 0x3);
+ if (value == 0)
+ *invalid = 1;
+
+ return value;
+}
/* Macros used to form opcodes. */
@@ -2645,6 +2837,13 @@ extract_vleil (unsigned long insn,
/* The mask for an VX form instruction. */
#define VX_MASK VX(0x3f, 0x7ff)
+/* A VX LSP form instruction. */
+#define VX_LSP(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xffff))
+
+/* The mask for an VX LSP form instruction. */
+#define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
+#define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
+
/* A VX_MASK with the VA field fixed. */
#define VXVA_MASK (VX_MASK | (0x1f << 16))
@@ -3125,6 +3324,7 @@ extract_vleil (unsigned long insn,
#define PPCVLE PPC_OPCODE_VLE
#define PPCHTM PPC_OPCODE_POWER8
#define E200Z4 PPC_OPCODE_E200Z4
+#define PPCLSP PPC_OPCODE_LSP
/* The list of embedded processors that use the embedded operand ordering
for the 3 operand dcbt and dcbtst instructions. */
#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
@@ -7134,6 +7334,686 @@ const struct powerpc_opcode vle_opcodes[] = {
{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
+/* by major opcode */
+{"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
+{"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
+{"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
+{"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
+{"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
+{"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
+{"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
+{"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}},
+{"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}},
+{"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
+{"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0, {RD, RA, RB, VX_OFF}},
+{"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
+{"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
+{"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
+{"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
+{"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
+{"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
+{"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
+{"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
+{"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
+{"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
+{"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
+{"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
+{"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
+{"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
+{"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
+{"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
+{"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
+{"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
+{"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
+{"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
+{"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
+{"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
+{"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
+{"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
+{"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
+{"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
+{"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
+{"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
+{"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
+{"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
+{"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
+{"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
+{"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
+{"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
+{"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
+{"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
+{"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
+{"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}},
+{"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
+{"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
+{"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
+{"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
+{"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
+{"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
+{"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
+{"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
+{"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
+{"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
+{"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
+{"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
+{"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
+{"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
+
{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
--
2.7.4