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FW: [PATCHv3] Implementing ARC NPS-400 Accelerator instructions cp16/cp32


Hi Claudiu,
Thanks for the feedback.

Changes at second version are: 
1. add dot at the end of sentence.
2. replace 8 spaces with tab.
3. I try this patch on last master ( commit e189bfe660d335f3b7c61446c9b5d3b0f0701606 ) and it was compiled ok.


Regards
Rinat


Load or store 16/32B Data from one address type to another.

gas/ChangeLog

	* testsuite/gas/arc/nps400-11.s: New file.
	* testsuite/gas/arc/nps400-11.d: New file.

include/ChangeLog

	* opcode/arc.h (insn_class_t): Add DMA class.

opcodes/ChangeLog

	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	(insert_nps_imm_offset): New function.
	(extract_nps_imm_offset): New function.
	(insert_nps_imm_entry): New function.
	(extract_nps_imm_entry): New function.

Signed-off-by: rinat zelig <rinat@mellanox.com>
---
 gas/ChangeLog                     |    5 +
 gas/testsuite/gas/arc/nps400-11.d |  303 ++++++++++++++++++++++++++++++++++++
 gas/testsuite/gas/arc/nps400-11.s |  308 +++++++++++++++++++++++++++++++++++++
 include/ChangeLog                 |    4 +
 include/opcode/arc.h              |    1 +
 opcodes/ChangeLog                 |    9 +
 opcodes/arc-nps400-tbl.h          |  191 +++++++++++++++++++++++
 opcodes/arc-opc.c                 |   82 ++++++++++-
 8 files changed, 900 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/arc/nps400-11.d
 create mode 100644 gas/testsuite/gas/arc/nps400-11.s

diff --git a/gas/testsuite/gas/arc/nps400-11.d b/gas/testsuite/gas/arc/nps400-11.d
new file mode 100644
index 0000000..bc50fbb
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-11.d
@@ -0,0 +1,303 @@
+#as: -mcpu=arc700 -mnps400
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+   0:	4a27 c222           	cp16\.na	\[cm:r1\],\[xa:r2\]
+   4:	4a27 c022           	cp16	\[cm:r1\],\[xa:r2\]
+   8:	4a27 c322           	cp32\.na	\[cm:r1\],\[xa:r2\]
+   c:	4a27 c122           	cp32	\[cm:r1\],\[xa:r2\]
+  10:	4a27 8222           	cp16\.na	\[cm:r1\],\[xa:r2,r1\]
+  14:	4a27 8022           	cp16	\[cm:r1\],\[xa:r2,r1\]
+  18:	4a27 8322           	cp32\.na	\[cm:r1\],\[xa:r2,r1\]
+  1c:	4a27 8122           	cp32	\[cm:r1\],\[xa:r2,r1\]
+  20:	4a27 4222           	cp16\.na	r2,\[cm:r1\],\[xa:r2\]
+  24:	4a27 4022           	cp16	r2,\[cm:r1\],\[xa:r2\]
+  28:	4a27 4322           	cp32\.na	r2,\[cm:r1\],\[xa:r2\]
+  2c:	4a27 4122           	cp32	r2,\[cm:r1\],\[xa:r2\]
+  30:	4a27 0222           	cp16\.na	r2,\[cm:r1\],\[xa:r2,r1\]
+  34:	4a27 0022           	cp16	r2,\[cm:r1\],\[xa:r2,r1\]
+  38:	4a27 0322           	cp32\.na	r2,\[cm:r1\],\[xa:r2,r1\]
+  3c:	4a27 0122           	cp32	r2,\[cm:r1\],\[xa:r2,r1\]
+  40:	4a27 c142           	cp32	\[cm:r1\],\[jid:r2\]
+  44:	4a27 4142           	cp32	r2,\[cm:r1\],\[jid:r2\]
+  48:	4947 c062           	cp16	\[cm:r2\],\[sd:r1,0x10,0\]
+  4c:	4947 c262           	cp16\.na	\[cm:r2\],\[sd:r1,0x10,0\]
+  50:	4947 4062           	cp16	r1,\[cm:r2\],\[sd:r1,0x10,0\]
+  54:	4947 4262           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x10,0\]
+  58:	4947 c066           	cp16	\[cm:r2\],\[sd:r1,0x20,0\]
+  5c:	4947 c266           	cp16\.na	\[cm:r2\],\[sd:r1,0x20,0\]
+  60:	4947 4066           	cp16	r1,\[cm:r2\],\[sd:r1,0x20,0\]
+  64:	4947 4266           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x20,0\]
+  68:	4947 c06a           	cp16	\[cm:r2\],\[sd:r1,0x40,0\]
+  6c:	4947 c26a           	cp16\.na	\[cm:r2\],\[sd:r1,0x40,0\]
+  70:	4947 406a           	cp16	r1,\[cm:r2\],\[sd:r1,0x40,0\]
+  74:	4947 426a           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x40,0\]
+  78:	4947 c06e           	cp16	\[cm:r2\],\[sd:r1,0x80,0\]
+  7c:	4947 c26e           	cp16\.na	\[cm:r2\],\[sd:r1,0x80,0\]
+  80:	4947 406e           	cp16	r1,\[cm:r2\],\[sd:r1,0x80,0\]
+  84:	4947 426e           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x80,0\]
+  88:	4947 c062           	cp16	\[cm:r2\],\[sd:r1,0x10,0\]
+  8c:	4947 c262           	cp16\.na	\[cm:r2\],\[sd:r1,0x10,0\]
+  90:	4947 4062           	cp16	r1,\[cm:r2\],\[sd:r1,0x10,0\]
+  94:	4947 4262           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x10,0\]
+  98:	4947 c462           	cp16	\[cm:r2\],\[sd:r1,0x10,0x10\]
+  9c:	4947 c662           	cp16\.na	\[cm:r2\],\[sd:r1,0x10,0x10\]
+  a0:	4947 4462           	cp16	r1,\[cm:r2\],\[sd:r1,0x10,0x10\]
+  a4:	4947 4662           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x10,0x10\]
+  a8:	4947 c862           	cp16	\[cm:r2\],\[sd:r1,0x10,0x20\]
+  ac:	4947 ca62           	cp16\.na	\[cm:r2\],\[sd:r1,0x10,0x20\]
+  b0:	4947 4862           	cp16	r1,\[cm:r2\],\[sd:r1,0x10,0x20\]
+  b4:	4947 4a62           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x10,0x20\]
+  b8:	4947 cc62           	cp16	\[cm:r2\],\[sd:r1,0x10,0x30\]
+  bc:	4947 ce62           	cp16\.na	\[cm:r2\],\[sd:r1,0x10,0x30\]
+  c0:	4947 4c62           	cp16	r1,\[cm:r2\],\[sd:r1,0x10,0x30\]
+  c4:	4947 4e62           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x10,0x30\]
+  c8:	4947 d062           	cp16	\[cm:r2\],\[sd:r1,0x10,0x40\]
+  cc:	4947 d262           	cp16\.na	\[cm:r2\],\[sd:r1,0x10,0x40\]
+  d0:	4947 5062           	cp16	r1,\[cm:r2\],\[sd:r1,0x10,0x40\]
+  d4:	4947 5262           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x10,0x40\]
+  d8:	4947 8062           	cp16	\[cm:r2\],\[sd:r1,0x10,0,r2\]
+  dc:	4947 8262           	cp16\.na	\[cm:r2\],\[sd:r1,0x10,0,r2\]
+  e0:	4947 0062           	cp16	r1,\[cm:r2\],\[sd:r1,0x10,0,r2\]
+  e4:	4947 0262           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x10,0,r2\]
+  e8:	4947 8066           	cp16	\[cm:r2\],\[sd:r1,0x20,0,r2\]
+  ec:	4947 8266           	cp16\.na	\[cm:r2\],\[sd:r1,0x20,0,r2\]
+  f0:	4947 0066           	cp16	r1,\[cm:r2\],\[sd:r1,0x20,0,r2\]
+  f4:	4947 0266           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x20,0,r2\]
+  f8:	4947 806a           	cp16	\[cm:r2\],\[sd:r1,0x40,0,r2\]
+  fc:	4947 826a           	cp16\.na	\[cm:r2\],\[sd:r1,0x40,0,r2\]
+ 100:	4947 006a           	cp16	r1,\[cm:r2\],\[sd:r1,0x40,0,r2\]
+ 104:	4947 026a           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x40,0,r2\]
+ 108:	4947 806e           	cp16	\[cm:r2\],\[sd:r1,0x80,0,r2\]
+ 10c:	4947 826e           	cp16\.na	\[cm:r2\],\[sd:r1,0x80,0,r2\]
+ 110:	4947 006e           	cp16	r1,\[cm:r2\],\[sd:r1,0x80,0,r2\]
+ 114:	4947 026e           	cp16\.na	r1,\[cm:r2\],\[sd:r1,0x80,0,r2\]
+ 118:	4947 c060           	cp16	\[cm:r2\],\[sd:r1,r2,r2\]
+ 11c:	4947 c260           	cp16\.na	\[cm:r2\],\[sd:r1,r2,r2\]
+ 120:	4947 4060           	cp16	r1,\[cm:r2\],\[sd:r1,r2,r2\]
+ 124:	4947 4260           	cp16\.na	r1,\[cm:r2\],\[sd:r1,r2,r2\]
+ 128:	4947 8060           	cp16	\[cm:r2\],\[sd:r1,r2,r2,r2\]
+ 12c:	4947 8260           	cp16\.na	\[cm:r2\],\[sd:r1,r2,r2,r2\]
+ 130:	4947 0060           	cp16	r1,\[cm:r2\],\[sd:r1,r2,r2,r2\]
+ 134:	4947 0260           	cp16\.na	r1,\[cm:r2\],\[sd:r1,r2,r2,r2\]
+ 138:	4947 c162           	cp32	\[cm:r2\],\[sd:r1,0x10,0\]
+ 13c:	4947 c362           	cp32\.na	\[cm:r2\],\[sd:r1,0x10,0\]
+ 140:	4947 4162           	cp32	r1,\[cm:r2\],\[sd:r1,0x10,0\]
+ 144:	4947 4362           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x10,0\]
+ 148:	4947 c166           	cp32	\[cm:r2\],\[sd:r1,0x20,0\]
+ 14c:	4947 c366           	cp32\.na	\[cm:r2\],\[sd:r1,0x20,0\]
+ 150:	4947 4166           	cp32	r1,\[cm:r2\],\[sd:r1,0x20,0\]
+ 154:	4947 4366           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x20,0\]
+ 158:	4947 c16a           	cp32	\[cm:r2\],\[sd:r1,0x40,0\]
+ 15c:	4947 c36a           	cp32\.na	\[cm:r2\],\[sd:r1,0x40,0\]
+ 160:	4947 416a           	cp32	r1,\[cm:r2\],\[sd:r1,0x40,0\]
+ 164:	4947 436a           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x40,0\]
+ 168:	4947 c16e           	cp32	\[cm:r2\],\[sd:r1,0x80,0\]
+ 16c:	4947 c36e           	cp32\.na	\[cm:r2\],\[sd:r1,0x80,0\]
+ 170:	4947 416e           	cp32	r1,\[cm:r2\],\[sd:r1,0x80,0\]
+ 174:	4947 436e           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x80,0\]
+ 178:	4947 c162           	cp32	\[cm:r2\],\[sd:r1,0x10,0\]
+ 17c:	4947 c362           	cp32\.na	\[cm:r2\],\[sd:r1,0x10,0\]
+ 180:	4947 4162           	cp32	r1,\[cm:r2\],\[sd:r1,0x10,0\]
+ 184:	4947 4362           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x10,0\]
+ 188:	4947 c562           	cp32	\[cm:r2\],\[sd:r1,0x10,0x10\]
+ 18c:	4947 c762           	cp32\.na	\[cm:r2\],\[sd:r1,0x10,0x10\]
+ 190:	4947 4562           	cp32	r1,\[cm:r2\],\[sd:r1,0x10,0x10\]
+ 194:	4947 4762           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x10,0x10\]
+ 198:	4947 c962           	cp32	\[cm:r2\],\[sd:r1,0x10,0x20\]
+ 19c:	4947 cb62           	cp32\.na	\[cm:r2\],\[sd:r1,0x10,0x20\]
+ 1a0:	4947 4962           	cp32	r1,\[cm:r2\],\[sd:r1,0x10,0x20\]
+ 1a4:	4947 4b62           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x10,0x20\]
+ 1a8:	4947 cd62           	cp32	\[cm:r2\],\[sd:r1,0x10,0x30\]
+ 1ac:	4947 cf62           	cp32\.na	\[cm:r2\],\[sd:r1,0x10,0x30\]
+ 1b0:	4947 4d62           	cp32	r1,\[cm:r2\],\[sd:r1,0x10,0x30\]
+ 1b4:	4947 4f62           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x10,0x30\]
+ 1b8:	4947 d162           	cp32	\[cm:r2\],\[sd:r1,0x10,0x40\]
+ 1bc:	4947 d362           	cp32\.na	\[cm:r2\],\[sd:r1,0x10,0x40\]
+ 1c0:	4947 5162           	cp32	r1,\[cm:r2\],\[sd:r1,0x10,0x40\]
+ 1c4:	4947 5362           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x10,0x40\]
+ 1c8:	4947 8162           	cp32	\[cm:r2\],\[sd:r1,0x10,0,r2\]
+ 1cc:	4947 8362           	cp32\.na	\[cm:r2\],\[sd:r1,0x10,0,r2\]
+ 1d0:	4947 0162           	cp32	r1,\[cm:r2\],\[sd:r1,0x10,0,r2\]
+ 1d4:	4947 0362           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x10,0,r2\]
+ 1d8:	4947 8166           	cp32	\[cm:r2\],\[sd:r1,0x20,0,r2\]
+ 1dc:	4947 8366           	cp32\.na	\[cm:r2\],\[sd:r1,0x20,0,r2\]
+ 1e0:	4947 0166           	cp32	r1,\[cm:r2\],\[sd:r1,0x20,0,r2\]
+ 1e4:	4947 0366           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x20,0,r2\]
+ 1e8:	4947 816a           	cp32	\[cm:r2\],\[sd:r1,0x40,0,r2\]
+ 1ec:	4947 836a           	cp32\.na	\[cm:r2\],\[sd:r1,0x40,0,r2\]
+ 1f0:	4947 016a           	cp32	r1,\[cm:r2\],\[sd:r1,0x40,0,r2\]
+ 1f4:	4947 036a           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x40,0,r2\]
+ 1f8:	4947 816e           	cp32	\[cm:r2\],\[sd:r1,0x80,0,r2\]
+ 1fc:	4947 836e           	cp32\.na	\[cm:r2\],\[sd:r1,0x80,0,r2\]
+ 200:	4947 016e           	cp32	r1,\[cm:r2\],\[sd:r1,0x80,0,r2\]
+ 204:	4947 036e           	cp32\.na	r1,\[cm:r2\],\[sd:r1,0x80,0,r2\]
+ 208:	4947 c160           	cp32	\[cm:r2\],\[sd:r1,r2,r2\]
+ 20c:	4947 c360           	cp32\.na	\[cm:r2\],\[sd:r1,r2,r2\]
+ 210:	4947 4160           	cp32	r1,\[cm:r2\],\[sd:r1,r2,r2\]
+ 214:	4947 4360           	cp32\.na	r1,\[cm:r2\],\[sd:r1,r2,r2\]
+ 218:	4947 8160           	cp32	\[cm:r2\],\[sd:r1,r2,r2,r2\]
+ 21c:	4947 8360           	cp32\.na	\[cm:r2\],\[sd:r1,r2,r2,r2\]
+ 220:	4947 0160           	cp32	r1,\[cm:r2\],\[sd:r1,r2,r2,r2\]
+ 224:	4947 0360           	cp32\.na	r1,\[cm:r2\],\[sd:r1,r2,r2,r2\]
+ 228:	4947 c082           	cp16	\[cm:r2\],\[xd:r1,0x10,0\]
+ 22c:	4947 c282           	cp16\.na	\[cm:r2\],\[xd:r1,0x10,0\]
+ 230:	4947 4082           	cp16	r1,\[cm:r2\],\[xd:r1,0x10,0\]
+ 234:	4947 4282           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x10,0\]
+ 238:	4947 c086           	cp16	\[cm:r2\],\[xd:r1,0x20,0\]
+ 23c:	4947 c286           	cp16\.na	\[cm:r2\],\[xd:r1,0x20,0\]
+ 240:	4947 4086           	cp16	r1,\[cm:r2\],\[xd:r1,0x20,0\]
+ 244:	4947 4286           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x20,0\]
+ 248:	4947 c08a           	cp16	\[cm:r2\],\[xd:r1,0x40,0\]
+ 24c:	4947 c28a           	cp16\.na	\[cm:r2\],\[xd:r1,0x40,0\]
+ 250:	4947 408a           	cp16	r1,\[cm:r2\],\[xd:r1,0x40,0\]
+ 254:	4947 428a           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x40,0\]
+ 258:	4947 c08e           	cp16	\[cm:r2\],\[xd:r1,0x80,0\]
+ 25c:	4947 c28e           	cp16\.na	\[cm:r2\],\[xd:r1,0x80,0\]
+ 260:	4947 408e           	cp16	r1,\[cm:r2\],\[xd:r1,0x80,0\]
+ 264:	4947 428e           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x80,0\]
+ 268:	4947 c082           	cp16	\[cm:r2\],\[xd:r1,0x10,0\]
+ 26c:	4947 c282           	cp16\.na	\[cm:r2\],\[xd:r1,0x10,0\]
+ 270:	4947 4082           	cp16	r1,\[cm:r2\],\[xd:r1,0x10,0\]
+ 274:	4947 4282           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x10,0\]
+ 278:	4947 c482           	cp16	\[cm:r2\],\[xd:r1,0x10,0x10\]
+ 27c:	4947 c682           	cp16\.na	\[cm:r2\],\[xd:r1,0x10,0x10\]
+ 280:	4947 4482           	cp16	r1,\[cm:r2\],\[xd:r1,0x10,0x10\]
+ 284:	4947 4682           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x10,0x10\]
+ 288:	4947 c882           	cp16	\[cm:r2\],\[xd:r1,0x10,0x20\]
+ 28c:	4947 ca82           	cp16\.na	\[cm:r2\],\[xd:r1,0x10,0x20\]
+ 290:	4947 4882           	cp16	r1,\[cm:r2\],\[xd:r1,0x10,0x20\]
+ 294:	4947 4a82           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x10,0x20\]
+ 298:	4947 cc82           	cp16	\[cm:r2\],\[xd:r1,0x10,0x30\]
+ 29c:	4947 ce82           	cp16\.na	\[cm:r2\],\[xd:r1,0x10,0x30\]
+ 2a0:	4947 4c82           	cp16	r1,\[cm:r2\],\[xd:r1,0x10,0x30\]
+ 2a4:	4947 4e82           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x10,0x30\]
+ 2a8:	4947 d082           	cp16	\[cm:r2\],\[xd:r1,0x10,0x40\]
+ 2ac:	4947 d282           	cp16\.na	\[cm:r2\],\[xd:r1,0x10,0x40\]
+ 2b0:	4947 5082           	cp16	r1,\[cm:r2\],\[xd:r1,0x10,0x40\]
+ 2b4:	4947 5282           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x10,0x40\]
+ 2b8:	4947 8082           	cp16	\[cm:r2\],\[xd:r1,0x10,0,r2\]
+ 2bc:	4947 8282           	cp16\.na	\[cm:r2\],\[xd:r1,0x10,0,r2\]
+ 2c0:	4947 0082           	cp16	r1,\[cm:r2\],\[xd:r1,0x10,0,r2\]
+ 2c4:	4947 0282           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x10,0,r2\]
+ 2c8:	4947 8086           	cp16	\[cm:r2\],\[xd:r1,0x20,0,r2\]
+ 2cc:	4947 8286           	cp16\.na	\[cm:r2\],\[xd:r1,0x20,0,r2\]
+ 2d0:	4947 0086           	cp16	r1,\[cm:r2\],\[xd:r1,0x20,0,r2\]
+ 2d4:	4947 0286           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x20,0,r2\]
+ 2d8:	4947 808a           	cp16	\[cm:r2\],\[xd:r1,0x40,0,r2\]
+ 2dc:	4947 828a           	cp16\.na	\[cm:r2\],\[xd:r1,0x40,0,r2\]
+ 2e0:	4947 008a           	cp16	r1,\[cm:r2\],\[xd:r1,0x40,0,r2\]
+ 2e4:	4947 028a           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x40,0,r2\]
+ 2e8:	4947 808e           	cp16	\[cm:r2\],\[xd:r1,0x80,0,r2\]
+ 2ec:	4947 828e           	cp16\.na	\[cm:r2\],\[xd:r1,0x80,0,r2\]
+ 2f0:	4947 008e           	cp16	r1,\[cm:r2\],\[xd:r1,0x80,0,r2\]
+ 2f4:	4947 028e           	cp16\.na	r1,\[cm:r2\],\[xd:r1,0x80,0,r2\]
+ 2f8:	4947 c080           	cp16	\[cm:r2\],\[xd:r1,r2,r2\]
+ 2fc:	4947 c280           	cp16\.na	\[cm:r2\],\[xd:r1,r2,r2\]
+ 300:	4947 4080           	cp16	r1,\[cm:r2\],\[xd:r1,r2,r2\]
+ 304:	4947 4280           	cp16\.na	r1,\[cm:r2\],\[xd:r1,r2,r2\]
+ 308:	4947 8080           	cp16	\[cm:r2\],\[xd:r1,r2,r2,r2\]
+ 30c:	4947 8280           	cp16\.na	\[cm:r2\],\[xd:r1,r2,r2,r2\]
+ 310:	4947 0080           	cp16	r1,\[cm:r2\],\[xd:r1,r2,r2,r2\]
+ 314:	4947 0280           	cp16\.na	r1,\[cm:r2\],\[xd:r1,r2,r2,r2\]
+ 318:	4947 c182           	cp32	\[cm:r2\],\[xd:r1,0x10,0\]
+ 31c:	4947 c382           	cp32\.na	\[cm:r2\],\[xd:r1,0x10,0\]
+ 320:	4947 4182           	cp32	r1,\[cm:r2\],\[xd:r1,0x10,0\]
+ 324:	4947 4382           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x10,0\]
+ 328:	4947 c186           	cp32	\[cm:r2\],\[xd:r1,0x20,0\]
+ 32c:	4947 c386           	cp32\.na	\[cm:r2\],\[xd:r1,0x20,0\]
+ 330:	4947 4186           	cp32	r1,\[cm:r2\],\[xd:r1,0x20,0\]
+ 334:	4947 4386           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x20,0\]
+ 338:	4947 c18a           	cp32	\[cm:r2\],\[xd:r1,0x40,0\]
+ 33c:	4947 c38a           	cp32\.na	\[cm:r2\],\[xd:r1,0x40,0\]
+ 340:	4947 418a           	cp32	r1,\[cm:r2\],\[xd:r1,0x40,0\]
+ 344:	4947 438a           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x40,0\]
+ 348:	4947 c18e           	cp32	\[cm:r2\],\[xd:r1,0x80,0\]
+ 34c:	4947 c38e           	cp32\.na	\[cm:r2\],\[xd:r1,0x80,0\]
+ 350:	4947 418e           	cp32	r1,\[cm:r2\],\[xd:r1,0x80,0\]
+ 354:	4947 438e           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x80,0\]
+ 358:	4947 c182           	cp32	\[cm:r2\],\[xd:r1,0x10,0\]
+ 35c:	4947 c382           	cp32\.na	\[cm:r2\],\[xd:r1,0x10,0\]
+ 360:	4947 4182           	cp32	r1,\[cm:r2\],\[xd:r1,0x10,0\]
+ 364:	4947 4382           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x10,0\]
+ 368:	4947 c582           	cp32	\[cm:r2\],\[xd:r1,0x10,0x10\]
+ 36c:	4947 c782           	cp32\.na	\[cm:r2\],\[xd:r1,0x10,0x10\]
+ 370:	4947 4582           	cp32	r1,\[cm:r2\],\[xd:r1,0x10,0x10\]
+ 374:	4947 4782           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x10,0x10\]
+ 378:	4947 c982           	cp32	\[cm:r2\],\[xd:r1,0x10,0x20\]
+ 37c:	4947 cb82           	cp32\.na	\[cm:r2\],\[xd:r1,0x10,0x20\]
+ 380:	4947 4982           	cp32	r1,\[cm:r2\],\[xd:r1,0x10,0x20\]
+ 384:	4947 4b82           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x10,0x20\]
+ 388:	4947 cd82           	cp32	\[cm:r2\],\[xd:r1,0x10,0x30\]
+ 38c:	4947 cf82           	cp32\.na	\[cm:r2\],\[xd:r1,0x10,0x30\]
+ 390:	4947 4d82           	cp32	r1,\[cm:r2\],\[xd:r1,0x10,0x30\]
+ 394:	4947 4f82           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x10,0x30\]
+ 398:	4947 d182           	cp32	\[cm:r2\],\[xd:r1,0x10,0x40\]
+ 39c:	4947 d382           	cp32\.na	\[cm:r2\],\[xd:r1,0x10,0x40\]
+ 3a0:	4947 5182           	cp32	r1,\[cm:r2\],\[xd:r1,0x10,0x40\]
+ 3a4:	4947 5382           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x10,0x40\]
+ 3a8:	4947 8182           	cp32	\[cm:r2\],\[xd:r1,0x10,0,r2\]
+ 3ac:	4947 8382           	cp32\.na	\[cm:r2\],\[xd:r1,0x10,0,r2\]
+ 3b0:	4947 0182           	cp32	r1,\[cm:r2\],\[xd:r1,0x10,0,r2\]
+ 3b4:	4947 0382           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x10,0,r2\]
+ 3b8:	4947 8186           	cp32	\[cm:r2\],\[xd:r1,0x20,0,r2\]
+ 3bc:	4947 8386           	cp32\.na	\[cm:r2\],\[xd:r1,0x20,0,r2\]
+ 3c0:	4947 0186           	cp32	r1,\[cm:r2\],\[xd:r1,0x20,0,r2\]
+ 3c4:	4947 0386           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x20,0,r2\]
+ 3c8:	4947 818a           	cp32	\[cm:r2\],\[xd:r1,0x40,0,r2\]
+ 3cc:	4947 838a           	cp32\.na	\[cm:r2\],\[xd:r1,0x40,0,r2\]
+ 3d0:	4947 018a           	cp32	r1,\[cm:r2\],\[xd:r1,0x40,0,r2\]
+ 3d4:	4947 038a           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x40,0,r2\]
+ 3d8:	4947 818e           	cp32	\[cm:r2\],\[xd:r1,0x80,0,r2\]
+ 3dc:	4947 838e           	cp32\.na	\[cm:r2\],\[xd:r1,0x80,0,r2\]
+ 3e0:	4947 018e           	cp32	r1,\[cm:r2\],\[xd:r1,0x80,0,r2\]
+ 3e4:	4947 038e           	cp32\.na	r1,\[cm:r2\],\[xd:r1,0x80,0,r2\]
+ 3e8:	4947 c180           	cp32	\[cm:r2\],\[xd:r1,r2,r2\]
+ 3ec:	4947 c380           	cp32\.na	\[cm:r2\],\[xd:r1,r2,r2\]
+ 3f0:	4947 4180           	cp32	r1,\[cm:r2\],\[xd:r1,r2,r2\]
+ 3f4:	4947 4380           	cp32\.na	r1,\[cm:r2\],\[xd:r1,r2,r2\]
+ 3f8:	4947 8180           	cp32	\[cm:r2\],\[xd:r1,r2,r2,r2\]
+ 3fc:	4947 8380           	cp32\.na	\[cm:r2\],\[xd:r1,r2,r2,r2\]
+ 400:	4947 0180           	cp32	r1,\[cm:r2\],\[xd:r1,r2,r2,r2\]
+ 404:	4947 0380           	cp32\.na	r1,\[cm:r2\],\[xd:r1,r2,r2,r2\]
+ 408:	4947 c023           	cp16	\[xa:r1\],\[cm:r2\]
+ 40c:	4947 c223           	cp16.na	\[xa:r1\],\[cm:r2\]
+ 410:	4947 c123           	cp32	\[xa:r1\],\[cm:r2\]
+ 414:	4947 c323           	cp32.na	\[xa:r1\],\[cm:r2\]
+ 418:	4947 c143           	cp32	\[jid:r1\],\[cm:r2\]
+ 41c:	4947 c467           	cp16	\[sd:r1,0x20,0x10\],\[cm:r2\]
+ 420:	4947 c667           	cp16.na	\[sd:r1,0x20,0x10\],\[cm:r2\]
+ 424:	4947 c487           	cp16	\[xd:r1,0x20,0x10\],\[cm:r2\]
+ 428:	4947 c687           	cp16.na	\[xd:r1,0x20,0x10\],\[cm:r2\]
+ 42c:	4947 c567           	cp32	\[sd:r1,0x20,0x10\],\[cm:r2\]
+ 430:	4947 c767           	cp32.na	\[sd:r1,0x20,0x10\],\[cm:r2\]
+ 434:	4947 c587           	cp32	\[xd:r1,0x20,0x10\],\[cm:r2\]
+ 438:	4947 c787           	cp32.na	\[xd:r1,0x20,0x10\],\[cm:r2\]
+ 43c:	4947 8467           	cp16	\[sd:r1,0x20,0x10,r2\],\[cm:r2\]
+ 440:	4947 8667           	cp16.na	\[sd:r1,0x20,0x10,r2\],\[cm:r2\]
+ 444:	4947 8487           	cp16	\[xd:r1,0x20,0x10,r2\],\[cm:r2\]
+ 448:	4947 8687           	cp16.na	\[xd:r1,0x20,0x10,r2\],\[cm:r2\]
+ 44c:	4947 8567           	cp32	\[sd:r1,0x20,0x10,r2\],\[cm:r2\]
+ 450:	4947 8767           	cp32.na	\[sd:r1,0x20,0x10,r2\],\[cm:r2\]
+ 454:	4947 8587           	cp32	\[xd:r1,0x20,0x10,r2\],\[cm:r2\]
+ 458:	4947 8787           	cp32.na	\[xd:r1,0x20,0x10,r2\],\[cm:r2\]
+ 45c:	4947 c061           	cp16	\[sd:r1,r2,r2\],\[cm:r2\]
+ 460:	4947 c261           	cp16.na	\[sd:r1,r2,r2\],\[cm:r2\]
+ 464:	4947 c081           	cp16	\[xd:r1,r2,r2\],\[cm:r2\]
+ 468:	4947 c281           	cp16.na	\[xd:r1,r2,r2\],\[cm:r2\]
+ 46c:	4947 c161           	cp32	\[sd:r1,r2,r2\],\[cm:r2\]
+ 470:	4947 c361           	cp32.na	\[sd:r1,r2,r2\],\[cm:r2\]
+ 474:	4947 c181           	cp32	\[xd:r1,r2,r2\],\[cm:r2\]
+ 478:	4947 c381           	cp32.na	\[xd:r1,r2,r2\],\[cm:r2\]
+ 47c:	4947 8061           	cp16	\[sd:r1,r2,r2,r2\],\[cm:r2\]
+ 480:	4947 8261           	cp16.na	\[sd:r1,r2,r2,r2\],\[cm:r2\]
+ 484:	4947 8081           	cp16	\[xd:r1,r2,r2,r2\],\[cm:r2\]
+ 488:	4947 8281           	cp16.na	\[xd:r1,r2,r2,r2\],\[cm:r2\]
+ 48c:	4947 8161           	cp32	\[sd:r1,r2,r2,r2\],\[cm:r2\]
+ 490:	4947 8361           	cp32.na	\[sd:r1,r2,r2,r2\],\[cm:r2\]
+ 494:	4947 8181           	cp32	\[xd:r1,r2,r2,r2\],\[cm:r2\]
+ 498:	4947 8381           	cp32.na	\[xd:r1,r2,r2,r2\],\[cm:r2\]
diff --git a/gas/testsuite/gas/arc/nps400-11.s b/gas/testsuite/gas/arc/nps400-11.s
new file mode 100644
index 0000000..47b5925
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-11.s
@@ -0,0 +1,308 @@
+        .text
+
+        ; cp16/cp32 xa
+        cp16.na  [cm:r1],[xa:r2]
+        cp16     [cm:r1],[xa:r2]
+        cp32.na  [cm:r1],[xa:r2]
+        cp32     [cm:r1],[xa:r2]
+        cp16.na  [cm:r1],[xa:r2,r1]
+        cp16     [cm:r1],[xa:r2,r1]
+        cp32.na  [cm:r1],[xa:r2,r1]
+        cp32     [cm:r1],[xa:r2,r1]
+        cp16.na r2,  [cm:r1],[xa:r2]
+        cp16   	r2,  [cm:r1],[xa:r2]
+        cp32.na r2,  [cm:r1],[xa:r2]
+        cp32    r2,  [cm:r1],[xa:r2]
+        cp16.na  r2,  [cm:r1],[xa:r2,r1]
+        cp16   	 r2,  [cm:r1],[xa:r2,r1]
+        cp32.na  r2,  [cm:r1],[xa:r2,r1]
+        cp32     r2,  [cm:r1],[xa:r2,r1]
+
+        ;; cp16/cp32 jid
+        cp32      [cm:r1],[jid:r2]
+        cp32  r2, [cm:r1],[jid:r2]
+
+        ;; cp16/cp32 sd
+        cp16   [cm:r2],[sd:r1,16,0]
+        cp16.na   [cm:r2],[sd:r1,16,0]
+        cp16   r1, [cm:r2],[sd:r1,16,0]
+        cp16.na   r1, [cm:r2],[sd:r1,16,0]
+        cp16   [cm:r2],[sd:r1,32,0]
+        cp16.na   [cm:r2],[sd:r1,32,0]
+        cp16   r1, [cm:r2],[sd:r1,32,0]
+        cp16.na   r1, [cm:r2],[sd:r1,32,0]
+        cp16   [cm:r2],[sd:r1,64,0]
+        cp16.na   [cm:r2],[sd:r1,64,0]
+        cp16   r1, [cm:r2],[sd:r1,64,0]
+        cp16.na   r1, [cm:r2],[sd:r1,64,0]
+        cp16   [cm:r2],[sd:r1,128,0]
+        cp16.na   [cm:r2],[sd:r1,128,0]
+        cp16   r1, [cm:r2],[sd:r1,128,0]
+        cp16.na   r1, [cm:r2],[sd:r1,128,0]
+        cp16   [cm:r2],[sd:r1,16,0]
+        cp16.na   [cm:r2],[sd:r1,16,0]
+        cp16   r1, [cm:r2],[sd:r1,16,0]
+        cp16.na   r1, [cm:r2],[sd:r1,16,0]
+        cp16   [cm:r2],[sd:r1,16,16]
+        cp16.na   [cm:r2],[sd:r1,16,16]
+        cp16   r1, [cm:r2],[sd:r1,16,16]
+        cp16.na   r1, [cm:r2],[sd:r1,16,16]
+        cp16   [cm:r2],[sd:r1,16,32]
+        cp16.na   [cm:r2],[sd:r1,16,32]
+        cp16   r1, [cm:r2],[sd:r1,16,32]
+        cp16.na   r1, [cm:r2],[sd:r1,16,32]
+        cp16   [cm:r2],[sd:r1,16,48]
+        cp16.na   [cm:r2],[sd:r1,16,48]
+        cp16   r1, [cm:r2],[sd:r1,16,48]
+        cp16.na   r1, [cm:r2],[sd:r1,16,48]
+        cp16   [cm:r2],[sd:r1,16,64]
+        cp16.na   [cm:r2],[sd:r1,16,64]
+        cp16   r1, [cm:r2],[sd:r1,16,64]
+        cp16.na   r1, [cm:r2],[sd:r1,16,64]
+        cp16   [cm:r2],[sd:r1,16,0, r2]
+        cp16.na   [cm:r2],[sd:r1,16,0, r2]
+        cp16   r1, [cm:r2],[sd:r1,16,0,r2]
+        cp16.na   r1, [cm:r2],[sd:r1,16,0,r2]
+        cp16   [cm:r2],[sd:r1,32,0, r2]
+        cp16.na   [cm:r2],[sd:r1,32,0, r2]
+        cp16   r1, [cm:r2],[sd:r1,32,0, r2]
+        cp16.na   r1, [cm:r2],[sd:r1,32,0, r2]
+        cp16   [cm:r2],[sd:r1,64,0, r2]
+        cp16.na   [cm:r2],[sd:r1,64,0, r2]
+        cp16   r1, [cm:r2],[sd:r1,64,0, r2]
+        cp16.na   r1, [cm:r2],[sd:r1,64,0, r2]
+        cp16   [cm:r2],[sd:r1,128,0, r2]
+        cp16.na   [cm:r2],[sd:r1,128,0, r2]
+        cp16   r1, [cm:r2],[sd:r1,128,0, r2]
+        cp16.na   r1, [cm:r2],[sd:r1,128,0, r2]
+        cp16   [cm:r2],[sd:r1,r2,r2]
+        cp16.na   [cm:r2],[sd:r1,r2,r2]
+        cp16   r1, [cm:r2],[sd:r1,r2,r2]
+        cp16.na   r1, [cm:r2],[sd:r1,r2,r2]
+        cp16   [cm:r2],[sd:r1,r2,r2,r2]
+        cp16.na   [cm:r2],[sd:r1,r2,r2,r2]
+        cp16   r1, [cm:r2],[sd:r1,r2,r2,r2]
+        cp16.na   r1, [cm:r2],[sd:r1,r2,r2,r2]
+        cp32   [cm:r2],[sd:r1,16,0]
+        cp32.na   [cm:r2],[sd:r1,16,0]
+        cp32   r1, [cm:r2],[sd:r1,16,0]
+        cp32.na   r1, [cm:r2],[sd:r1,16,0]
+        cp32   [cm:r2],[sd:r1,32,0]
+        cp32.na   [cm:r2],[sd:r1,32,0]
+        cp32   r1, [cm:r2],[sd:r1,32,0]
+        cp32.na   r1, [cm:r2],[sd:r1,32,0]
+        cp32   [cm:r2],[sd:r1,64,0]
+        cp32.na   [cm:r2],[sd:r1,64,0]
+        cp32   r1, [cm:r2],[sd:r1,64,0]
+        cp32.na   r1, [cm:r2],[sd:r1,64,0]
+        cp32   [cm:r2],[sd:r1,128,0]
+        cp32.na   [cm:r2],[sd:r1,128,0]
+        cp32   r1, [cm:r2],[sd:r1,128,0]
+        cp32.na   r1, [cm:r2],[sd:r1,128,0]
+        cp32   [cm:r2],[sd:r1,16,0]
+        cp32.na   [cm:r2],[sd:r1,16,0]
+        cp32   r1, [cm:r2],[sd:r1,16,0]
+        cp32.na   r1, [cm:r2],[sd:r1,16,0]
+        cp32   [cm:r2],[sd:r1,16,16]
+        cp32.na   [cm:r2],[sd:r1,16,16]
+        cp32   r1, [cm:r2],[sd:r1,16,16]
+        cp32.na   r1, [cm:r2],[sd:r1,16,16]
+        cp32   [cm:r2],[sd:r1,16,32]
+        cp32.na   [cm:r2],[sd:r1,16,32]
+        cp32   r1, [cm:r2],[sd:r1,16,32]
+        cp32.na   r1, [cm:r2],[sd:r1,16,32]
+        cp32   [cm:r2],[sd:r1,16,48]
+        cp32.na   [cm:r2],[sd:r1,16,48]
+        cp32   r1, [cm:r2],[sd:r1,16,48]
+        cp32.na   r1, [cm:r2],[sd:r1,16,48]
+        cp32   [cm:r2],[sd:r1,16,64]
+        cp32.na   [cm:r2],[sd:r1,16,64]
+        cp32   r1, [cm:r2],[sd:r1,16,64]
+        cp32.na   r1, [cm:r2],[sd:r1,16,64]
+        cp32   [cm:r2],[sd:r1,16,0, r2]
+        cp32.na   [cm:r2],[sd:r1,16,0, r2]
+        cp32   r1, [cm:r2],[sd:r1,16,0,r2]
+        cp32.na   r1, [cm:r2],[sd:r1,16,0,r2]
+        cp32   [cm:r2],[sd:r1,32,0, r2]
+        cp32.na   [cm:r2],[sd:r1,32,0, r2]
+        cp32   r1, [cm:r2],[sd:r1,32,0, r2]
+        cp32.na   r1, [cm:r2],[sd:r1,32,0, r2]
+        cp32   [cm:r2],[sd:r1,64,0, r2]
+        cp32.na   [cm:r2],[sd:r1,64,0, r2]
+        cp32   r1, [cm:r2],[sd:r1,64,0, r2]
+        cp32.na   r1, [cm:r2],[sd:r1,64,0, r2]
+        cp32   [cm:r2],[sd:r1,128,0, r2]
+        cp32.na   [cm:r2],[sd:r1,128,0, r2]
+        cp32   r1, [cm:r2],[sd:r1,128,0, r2]
+        cp32.na   r1, [cm:r2],[sd:r1,128,0, r2]
+        cp32   [cm:r2],[sd:r1,r2,r2]
+        cp32.na   [cm:r2],[sd:r1,r2,r2]
+        cp32   r1, [cm:r2],[sd:r1,r2,r2]
+        cp32.na   r1, [cm:r2],[sd:r1,r2,r2]
+        cp32   [cm:r2],[sd:r1,r2,r2,r2]
+        cp32.na   [cm:r2],[sd:r1,r2,r2,r2]
+        cp32   r1, [cm:r2],[sd:r1,r2,r2,r2]
+        cp32.na   r1, [cm:r2],[sd:r1,r2,r2,r2]
+        ; cp16/cp32 xd
+        cp16   [cm:r2],[xd:r1,16,0]
+        cp16.na   [cm:r2],[xd:r1,16,0]
+        cp16   r1, [cm:r2],[xd:r1,16,0]
+        cp16.na   r1, [cm:r2],[xd:r1,16,0]
+        cp16   [cm:r2],[xd:r1,32,0]
+        cp16.na   [cm:r2],[xd:r1,32,0]
+        cp16   r1, [cm:r2],[xd:r1,32,0]
+        cp16.na   r1, [cm:r2],[xd:r1,32,0]
+        cp16   [cm:r2],[xd:r1,64,0]
+        cp16.na   [cm:r2],[xd:r1,64,0]
+        cp16   r1, [cm:r2],[xd:r1,64,0]
+        cp16.na   r1, [cm:r2],[xd:r1,64,0]
+        cp16   [cm:r2],[xd:r1,128,0]
+        cp16.na   [cm:r2],[xd:r1,128,0]
+        cp16   r1, [cm:r2],[xd:r1,128,0]
+        cp16.na   r1, [cm:r2],[xd:r1,128,0]
+        cp16   [cm:r2],[xd:r1,16,0]
+        cp16.na   [cm:r2],[xd:r1,16,0]
+        cp16   r1, [cm:r2],[xd:r1,16,0]
+        cp16.na   r1, [cm:r2],[xd:r1,16,0]
+        cp16   [cm:r2],[xd:r1,16,16]
+        cp16.na   [cm:r2],[xd:r1,16,16]
+        cp16   r1, [cm:r2],[xd:r1,16,16]
+        cp16.na   r1, [cm:r2],[xd:r1,16,16]
+        cp16   [cm:r2],[xd:r1,16,32]
+        cp16.na   [cm:r2],[xd:r1,16,32]
+        cp16   r1, [cm:r2],[xd:r1,16,32]
+        cp16.na   r1, [cm:r2],[xd:r1,16,32]
+        cp16   [cm:r2],[xd:r1,16,48]
+        cp16.na   [cm:r2],[xd:r1,16,48]
+        cp16   r1, [cm:r2],[xd:r1,16,48]
+        cp16.na   r1, [cm:r2],[xd:r1,16,48]
+        cp16   [cm:r2],[xd:r1,16,64]
+        cp16.na   [cm:r2],[xd:r1,16,64]
+        cp16   r1, [cm:r2],[xd:r1,16,64]
+        cp16.na   r1, [cm:r2],[xd:r1,16,64]
+        cp16   [cm:r2],[xd:r1,16,0, r2]
+        cp16.na   [cm:r2],[xd:r1,16,0, r2]
+        cp16   r1, [cm:r2],[xd:r1,16,0,r2]
+        cp16.na   r1, [cm:r2],[xd:r1,16,0,r2]
+        cp16   [cm:r2],[xd:r1,32,0, r2]
+        cp16.na   [cm:r2],[xd:r1,32,0, r2]
+        cp16   r1, [cm:r2],[xd:r1,32,0, r2]
+        cp16.na   r1, [cm:r2],[xd:r1,32,0, r2]
+        cp16   [cm:r2],[xd:r1,64,0, r2]
+        cp16.na   [cm:r2],[xd:r1,64,0, r2]
+        cp16   r1, [cm:r2],[xd:r1,64,0, r2]
+        cp16.na   r1, [cm:r2],[xd:r1,64,0, r2]
+        cp16   [cm:r2],[xd:r1,128,0, r2]
+        cp16.na   [cm:r2],[xd:r1,128,0, r2]
+        cp16   r1, [cm:r2],[xd:r1,128,0, r2]
+        cp16.na   r1, [cm:r2],[xd:r1,128,0, r2]
+        cp16   [cm:r2],[xd:r1,r2,r2]
+        cp16.na   [cm:r2],[xd:r1,r2,r2]
+        cp16   r1, [cm:r2],[xd:r1,r2,r2]
+        cp16.na   r1, [cm:r2],[xd:r1,r2,r2]
+        cp16   [cm:r2],[xd:r1,r2,r2,r2]
+        cp16.na   [cm:r2],[xd:r1,r2,r2,r2]
+        cp16   r1, [cm:r2],[xd:r1,r2,r2,r2]
+        cp16.na   r1, [cm:r2],[xd:r1,r2,r2,r2]
+        cp32   [cm:r2],[xd:r1,16,0]
+        cp32.na   [cm:r2],[xd:r1,16,0]
+        cp32   r1, [cm:r2],[xd:r1,16,0]
+        cp32.na   r1, [cm:r2],[xd:r1,16,0]
+        cp32   [cm:r2],[xd:r1,32,0]
+        cp32.na   [cm:r2],[xd:r1,32,0]
+        cp32   r1, [cm:r2],[xd:r1,32,0]
+        cp32.na   r1, [cm:r2],[xd:r1,32,0]
+        cp32   [cm:r2],[xd:r1,64,0]
+        cp32.na   [cm:r2],[xd:r1,64,0]
+        cp32   r1, [cm:r2],[xd:r1,64,0]
+        cp32.na   r1, [cm:r2],[xd:r1,64,0]
+        cp32   [cm:r2],[xd:r1,128,0]
+        cp32.na   [cm:r2],[xd:r1,128,0]
+        cp32   r1, [cm:r2],[xd:r1,128,0]
+        cp32.na   r1, [cm:r2],[xd:r1,128,0]
+        cp32   [cm:r2],[xd:r1,16,0]
+        cp32.na   [cm:r2],[xd:r1,16,0]
+        cp32   r1, [cm:r2],[xd:r1,16,0]
+        cp32.na   r1, [cm:r2],[xd:r1,16,0]
+        cp32   [cm:r2],[xd:r1,16,16]
+        cp32.na   [cm:r2],[xd:r1,16,16]
+        cp32   r1, [cm:r2],[xd:r1,16,16]
+        cp32.na   r1, [cm:r2],[xd:r1,16,16]
+        cp32   [cm:r2],[xd:r1,16,32]
+        cp32.na   [cm:r2],[xd:r1,16,32]
+        cp32   r1, [cm:r2],[xd:r1,16,32]
+        cp32.na   r1, [cm:r2],[xd:r1,16,32]
+        cp32   [cm:r2],[xd:r1,16,48]
+        cp32.na   [cm:r2],[xd:r1,16,48]
+        cp32   r1, [cm:r2],[xd:r1,16,48]
+        cp32.na   r1, [cm:r2],[xd:r1,16,48]
+        cp32   [cm:r2],[xd:r1,16,64]
+        cp32.na   [cm:r2],[xd:r1,16,64]
+        cp32   r1, [cm:r2],[xd:r1,16,64]
+        cp32.na   r1, [cm:r2],[xd:r1,16,64]
+        cp32   [cm:r2],[xd:r1,16,0, r2]
+        cp32.na   [cm:r2],[xd:r1,16,0, r2]
+        cp32   r1, [cm:r2],[xd:r1,16,0,r2]
+        cp32.na   r1, [cm:r2],[xd:r1,16,0,r2]
+        cp32   [cm:r2],[xd:r1,32,0, r2]
+        cp32.na   [cm:r2],[xd:r1,32,0, r2]
+        cp32   r1, [cm:r2],[xd:r1,32,0, r2]
+        cp32.na   r1, [cm:r2],[xd:r1,32,0, r2]
+        cp32   [cm:r2],[xd:r1,64,0, r2]
+        cp32.na   [cm:r2],[xd:r1,64,0, r2]
+        cp32   r1, [cm:r2],[xd:r1,64,0, r2]
+        cp32.na   r1, [cm:r2],[xd:r1,64,0, r2]
+        cp32   [cm:r2],[xd:r1,128,0, r2]
+        cp32.na   [cm:r2],[xd:r1,128,0, r2]
+        cp32   r1, [cm:r2],[xd:r1,128,0, r2]
+        cp32.na   r1, [cm:r2],[xd:r1,128,0, r2]
+        cp32   [cm:r2],[xd:r1,r2,r2]
+        cp32.na   [cm:r2],[xd:r1,r2,r2]
+        cp32   r1, [cm:r2],[xd:r1,r2,r2]
+        cp32.na   r1, [cm:r2],[xd:r1,r2,r2]
+        cp32   [cm:r2],[xd:r1,r2,r2,r2]
+        cp32.na   [cm:r2],[xd:r1,r2,r2,r2]
+        cp32   r1, [cm:r2],[xd:r1,r2,r2,r2]
+        cp32.na   r1, [cm:r2],[xd:r1,r2,r2,r2]
+        ;cp16/32 cm to xa
+        cp16 [xa:r1],[cm:r2]
+        cp16.na [xa:r1],[cm:r2]
+        cp32 [xa:r1],[cm:r2]
+        cp32.na [xa:r1],[cm:r2]
+        cp32 [jid:r1],[cm:r2]
+
+        cp16 [sd:r1,0x20,0x10],[cm:r2]
+        cp16.na [sd:r1,0x20,0x10],[cm:r2]
+        cp16 [xd:r1,0x20,0x10],[cm:r2]
+        cp16.na [xd:r1,0x20,0x10],[cm:r2]
+        cp32 [sd:r1,0x20,0x10],[cm:r2]
+        cp32.na [sd:r1,0x20,0x10],[cm:r2]
+        cp32 [xd:r1,0x20,0x10],[cm:r2]
+        cp32.na [xd:r1,0x20,0x10],[cm:r2]
+
+        cp16 [sd:r1,0x20,0x10,r2],[cm:r2]
+        cp16.na [sd:r1,0x20,0x10,r2],[cm:r2]
+        cp16 [xd:r1,0x20,0x10,r2],[cm:r2]
+        cp16.na [xd:r1,0x20,0x10,r2],[cm:r2]
+        cp32 [sd:r1,0x20,0x10,r2],[cm:r2]
+        cp32.na [sd:r1,0x20,0x10,r2],[cm:r2]
+        cp32 [xd:r1,0x20,0x10,r2],[cm:r2]
+        cp32.na [xd:r1,0x20,0x10,r2],[cm:r2]
+
+        cp16 [sd:r1,r2,r2],[cm:r2]
+        cp16.na [sd:r1,r2,r2],[cm:r2]
+        cp16 [xd:r1,r2,r2],[cm:r2]
+        cp16.na [xd:r1,r2,r2],[cm:r2]
+        cp32 [sd:r1,r2,r2],[cm:r2]
+        cp32.na [sd:r1,r2,r2],[cm:r2]
+        cp32 [xd:r1,r2,r2],[cm:r2]
+        cp32.na [xd:r1,r2,r2],[cm:r2]
+
+        cp16 [sd:r1,r2,r2,r2],[cm:r2]
+        cp16.na [sd:r1,r2,r2,r2],[cm:r2]
+        cp16 [xd:r1,r2,r2,r2],[cm:r2]
+        cp16.na [xd:r1,r2,r2,r2],[cm:r2]
+        cp32 [sd:r1,r2,r2,r2],[cm:r2]
+        cp32.na [sd:r1,r2,r2,r2],[cm:r2]
+        cp32 [xd:r1,r2,r2,r2],[cm:r2]
+        cp32.na [xd:r1,r2,r2,r2],[cm:r2]
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index f263fff..3914dc0 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -53,6 +53,7 @@ typedef enum
   BRCC,
   CONTROL,
   DIVREM,
+  DMA,
   DPI,
   DSP,
   EI,
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index bfc2dee..9952fb2 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -714,6 +714,197 @@ XLDST_LIKE("xst", 0xe)
 /* dcmac  a,[cm:A],[cm:b],size */
 { "dcmac", 0x500007c023000000, 0xf80007ffffc00000, ARC_OPCODE_ARC700, PROTOCOL_DECODE, NPS400, { NPS_RA_64, BRAKET, NPS_CM, COLON, NPS_UIMM16_0_64, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_RBdouble_64, BRAKETdup, NPS_PROTO_SIZE }, { 0 }},
 
+/* Aligned Copy 16/32 Byte Instructions.  */
+
+/* cp16<.na> dst, [cm:src2], [xa:src1] */
+{ "cp16", 0x48074022, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> dst, [cm:src2], [xa:src1] */
+{ "cp32", 0x48074122, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [cm:src2], [xa:src1] */
+{ "cp16", 0x4807c022, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [cm:src2], [xa:src1] */
+{ "cp32", 0x4807c122, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> dst, [cm:src2], [xa:src1,src2] */
+{ "cp16", 0x48070022, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> dst, [cm:src2], [xa:src1,src2] */
+{ "cp32", 0x48070122, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [cm:src2], [xa:src1,src2] */
+{ "cp16", 0x48078022, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [cm:src2], [xa:src1,src2] */
+{ "cp32", 0x48078122, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32 [cm:src2], [jid:src1] */
+{ "cp32", 0x4807c142, 0xf80fffff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_JID, COLON, NPS_DPI_SRC1_3B, BRAKETdup }, { 0 }},
+
+/* cp32 dst, [cm:src2], [jid:src1] */
+{ "cp32", 0x48074142, 0xf80fffff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_JID, COLON, NPS_DPI_SRC1_3B, BRAKETdup }, { 0 }},
+
+/* cp16<.na> [cm:src2],[sd:src1,entry,off] */
+{ "cp16", 0x4807c062, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [cm:src2],[sd:src1,entry,off] */
+{ "cp32", 0x4807c162, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> dst, [cm:src2],[sd:src1,entry,off] */
+{ "cp16", 0x48074062, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> dst, [cm:src2],[sd:src1,entry,off] */
+{ "cp32", 0x48074162, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [cm:src2],[sd:src1,entry,off, src2] */
+{ "cp16", 0x48078062, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [cm:src2],[sd:src1,entry,off, src2] */
+{ "cp32", 0x48078162, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> dst, [cm:src2],[sd:src1,entry,off,src2] */
+{ "cp16", 0x48070062, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> dst, [cm:src2],[sd:src1,entry,off,src2] */
+{ "cp32", 0x48070162, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [cm:src2],[sd:src1,src2, src2] */
+{ "cp16", 0x4807c060, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [cm:src2],[sd:src1,src2, src2] */
+{ "cp32", 0x4807c160, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> dst, [cm:src2],[sd:src1,src2,src2] */
+{ "cp16", 0x48074060, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> dst, [cm:src2],[sd:src1,src2,src2] */
+{ "cp32", 0x48074160, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [cm:src2],[sd:src1,src2,src2,src2] */
+{ "cp16", 0x48078060, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [cm:src2],[sd:src1,src2,src2,src2] */
+{ "cp32", 0x48078160, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> dst, [cm:src2],[sd:src1,src2,src2,src2] */
+{ "cp16", 0x48070060, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> dst, [cm:src2],[sd:src1,src2,src2,src2] */
+{ "cp32", 0x48070160, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [cm:src2],[xd:src1,entry,off] */
+{ "cp16", 0x4807c082, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [cm:src2],[xd:src1,entry,off] */
+{ "cp32", 0x4807c182, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> dst, [cm:src2],[xd:src1,entry,off] */
+{ "cp16", 0x48074082, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> dst, [cm:src2],[xd:src1,entry,off] */
+{ "cp32", 0x48074182, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [cm:src2],[xd:src1,entry,off, src2] */
+{ "cp16", 0x48078082, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [cm:src2],[xd:src1,entry,off, src2] */
+{ "cp32", 0x48078182, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> dst, [cm:src2],[xd:src1,entry,off,src2] */
+{ "cp16", 0x48070082, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> dst, [cm:src2],[xd:src1,entry,off,src2] */
+{ "cp32", 0x48070182, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [cm:src2],[xd:src1,src2, src2] */
+{ "cp16", 0x4807c080, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [cm:src2],[xd:src1,src2, src2] */
+{ "cp32", 0x4807c180, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> dst, [cm:src2],[xd:src1,src2,src2] */
+{ "cp16", 0x48074080, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> dst, [cm:src2],[xd:src1,src2,src2] */
+{ "cp32", 0x48074180, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [cm:src2],[xd:src1,src2,src2,src2] */
+{ "cp16", 0x48078080, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [cm:src2],[xd:src1,src2,src2,src2] */
+{ "cp32", 0x48078180, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> dst, [cm:src2],[xd:src1,src2,src2,src2] */
+{ "cp16", 0x48070080, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> dst, [cm:src2],[xd:src1,src2,src2,src2] */
+{ "cp32", 0x48070180, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [xa:src1], [cm:src2] */
+{ "cp16", 0x4807c023, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [xa:src1], [cm:src2] */
+{ "cp32", 0x4807c123, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [xa:src1,src2], [cm:src2] */
+{ "cp16", 0x48078023, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [xa:src1,src2], [cm:src2] */
+{ "cp32", 0x48078123, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XA, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32 [jid:src1], [cm:src2] */
+{ "cp32", 0x4807c143, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_JID, COLON, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { 0 }},
+
+/* cp16<.na> [sd:src1,entry,offset],[cm:src2] */
+{ "cp16", 0x4807c063, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [xd:src1,entry,offset], [cm:src2] */
+{ "cp16", 0x4807c083, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [sd:src1,entry,offset], [cm:src2] */
+{ "cp32", 0x4807c163, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [xd:src1,entry,offset], [cm:src2] */
+{ "cp32", 0x4807c183, 0xf80fc1e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [sd:src1,entry,offset,src2],[cm:src2] */
+{ "cp16", 0x48078063, 0xf80f81e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [xd:src1,entry,offset,src2],[cm:src2] */
+{ "cp16", 0x48078083, 0xf80f81e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [sd:src1,entry,offset,src2],[cm:src2] */
+{ "cp32", 0x48078163, 0xf80f81e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [xd:src1,entry,offset,src2],[cm:src2] */
+{ "cp32", 0x48078183, 0xf80f81e3, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [sd:src1,src2,src2], [cm:src2] */
+{ "cp16", 0x4807c061, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [xd:src1,src2,src2], [cm:src2] */
+{ "cp16", 0x4807c081, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [sd:src1,src2,src2], [cm:src2] */
+{ "cp32", 0x4807c161, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [xd:src1,src2,src2], [cm:src2] */
+{ "cp32", 0x4807c181, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [sd:src1,src2,src2,src2], [cm:src2] */
+{ "cp16", 0x48078061, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp16<.na> [xd:src1,src2,src2,src2], [cm:src2] */
+{ "cp16", 0x48078081, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [sd:src1,src2,src2,src2], [cm:src2] */
+{ "cp32", 0x48078161, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_SD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* cp32<.na> [xd:src1,src2,src2,src2], [cm:src2] */
+{ "cp32", 0x48078181, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+
 /* Atomic Operations.  */
 
 /* exc<.di><.f> a,a,[xa:b] */
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 2d72b12..ade0ada 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -832,6 +832,70 @@ extract_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED,
   return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
 }
 
+static unsigned int
+insert_nps_imm_offset (unsigned insn ATTRIBUTE_UNUSED,
+			int value ATTRIBUTE_UNUSED,
+			const char **errmsg ATTRIBUTE_UNUSED)
+{
+  switch (value)
+    {
+    case 0:
+    case 16:
+    case 32:
+    case 48:
+    case 64:
+      value = value >> 4;
+      break;
+    default:
+      *errmsg = _("Invalid position, should be 0, 16, 32, 48 or 64.");
+      value = 0;
+    }
+  insn |= (value << 10);
+  return insn;
+}
+
+static int
+extract_nps_imm_offset (unsigned insn ATTRIBUTE_UNUSED,
+				bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 10) & 0x7) * 16;
+}
+
+static unsigned int
+insert_nps_imm_entry (unsigned insn ATTRIBUTE_UNUSED,
+				int value ATTRIBUTE_UNUSED,
+				const char **errmsg ATTRIBUTE_UNUSED)
+{
+  switch (value)
+    {
+    case 16:
+      value = 0;
+      break;
+    case 32:
+      value = 1;
+      break;
+    case 64:
+      value = 2;
+      break;
+    case 128:
+    value = 3;
+    break;
+    default:
+      *errmsg = _("Invalid position, should be 16, 32, 64 or 128.");
+      value = 0;
+    }
+  insn |= (value << 2);
+  return insn;
+}
+
+static int
+extract_nps_imm_entry (unsigned insn ATTRIBUTE_UNUSED,
+				bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int imm_entry = ((insn >> 2) & 0x7);
+  return (1 << (imm_entry + 4));
+}
+
 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT)         \
 static unsigned long long                                               \
 insert_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED,      \
@@ -1301,7 +1365,10 @@ const struct arc_flag_operand arc_flag_operands[] =
 #define F_NPS_CL (F_NE + 1)
   { "cl", 0, 0, 0, 1 },
 
-#define F_NPS_FLAG (F_NPS_CL + 1)
+#define F_NPS_NA (F_NPS_CL + 1)
+  { "na", 1, 1, 9, 1 },
+
+#define F_NPS_FLAG (F_NPS_NA + 1)
   { "f", 1, 1, 20, 1 },
 
 #define F_NPS_R     (F_NPS_FLAG + 1)
@@ -1513,7 +1580,10 @@ const struct arc_flag_class arc_flag_classes[] =
 #define C_NPS_CL     (C_NE + 1)
   { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
 
-#define C_NPS_F     (C_NPS_CL + 1)
+#define C_NPS_NA     (C_NPS_CL + 1)
+  { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
+
+#define C_NPS_F     (C_NPS_NA + 1)
   { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
 
 #define C_NPS_R     (C_NPS_F + 1)
@@ -2207,7 +2277,13 @@ const struct arc_operand arc_operands[] =
 #define NPS_PMU_NUM_JOB     (NPS_PMU_NXT_DST + 1)
   { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job },
 
-#define NPS_R_DST_3B_48	(NPS_PMU_NUM_JOB + 1)
+#define NPS_DMA_IMM_ENTRY  (NPS_PMU_NUM_JOB + 1)
+  { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_entry, extract_nps_imm_entry },
+
+#define NPS_DMA_IMM_OFFSET  (NPS_DMA_IMM_ENTRY + 1)
+  { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_offset, extract_nps_imm_offset },
+
+#define NPS_R_DST_3B_48	(NPS_DMA_IMM_OFFSET + 1)
   { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
 
 #define NPS_R_SRC1_3B_48	(NPS_R_DST_3B_48 + 1)
-- 
1.7.1


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