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Re: [committed, PATCH] Add support for Intel CET instructions

On Mon, Mar 6, 2017 at 3:28 PM, H.J. Lu <hongjiu.lu@intel.com> wrote:
> Support Intel Control-flow Enforcement Technology (CET) instructions:
>
> https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
>
> gas/
>
>         * config/tc-i386.c (cpu_arch): Add .cet.
>         * doc/c-i386.texi: Document cet.
>         * testsuite/gas/i386/cet-intel.d: New file.
>         * testsuite/gas/i386/cet.d: Likewise.
>         * testsuite/gas/i386/cet.s: Likewise.
>         * testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
>         * testsuite/gas/i386/x86-64-cet.d: Likewise.
>         * testsuite/gas/i386/x86-64-cet.s: Likewise.
>         * testsuite/gas/i386/i386.exp: Run Intel CET tests.
>
> opcodes/
>
>         * i386-dis.c (REG_0F1E_MOD_3): New enum.
>         (MOD_0F1E_PREFIX_1): Likewise.
>         (MOD_0F38F5_PREFIX_2): Likewise.
>         (MOD_0F38F6_PREFIX_0): Likewise.
>         (RM_0F1E_MOD_3_REG_7): Likewise.
>         (PREFIX_MOD_0_0F01_REG_5): Likewise.
>         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
>         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
>         (PREFIX_0F1E): Likewise.
>         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
>         (PREFIX_0F38F5): Likewise.
>         (dis386_twobyte): Use PREFIX_0F1E.
>         (reg_table): Add REG_0F1E_MOD_3.
>         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
>         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
>         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
>         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
>         (three_byte_table): Use PREFIX_0F38F5.
>         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
>         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
>         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
>         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
>         PREFIX_MOD_3_0F01_REG_5_RM_2.
>         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
>         (cpu_flags): Add CpuCET.
>         * i386-opc.h (CpuCET): New enum.
>         (CpuUnused): Commented out.
>         (i386_cpu_flags): Add cpucet.
>         * i386-opc.tbl: Add Intel CET instructions.
>         * i386-init.h: Regenerated.
>         * i386-tbl.h: Likewise.


I checked in this to fix a typo.

-- 
H.J.

From c1fe188b154a4e81372629316be3d3a7820efdac Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 9 Mar 2017 07:43:48 -0800
Subject: [PATCH] Use CpuCET on rdsspq

	* i386-opc.tbl: Use CpuCET on rdsspq.
	* i386-tbl.h: Regenerated.
---
 opcodes/ChangeLog    | 5 +++++
 opcodes/i386-opc.tbl | 2 +-
 opcodes/i386-tbl.h   | 2 +-
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 52b6a92..0eae000 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-opc.tbl: Use CpuCET on rdsspq.
+	* i386-tbl.h: Regenerated.
+
 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 
 	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 4c259d5..1e16932 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -6002,7 +6002,7 @@ ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_
 incsspd, 0, 0xf30f01e9, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 incsspq, 0, 0xf30f01e9, None, 3, CpuCET|Cpu64, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { 0 }
 rdsspd, 1, 0xf30f1e, 0x1, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
-rdsspq, 1, 0xf30f1e, 0x1, 2, CpuRDPID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
+rdsspq, 1, 0xf30f1e, 0x1, 2, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
 savessp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 rstorssp, 1, 0xf30f01, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 wrssd, 2, 0x0f38f6, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 17033d2..eaf3a40 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -91946,7 +91946,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
+        0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-- 
2.9.3
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