From 2f5749790ec23114d57517a6ed53fe6a1282accb Mon Sep 17 00:00:00 2001
From: Alexander Fomin <alexander.fomin@intel.com>
Date: Fri, 10 Jun 2016 15:17:04 +0300
Subject: [PATCH 2/2] Enable Intel AVX512_4VNNIW instructions.

2016-09-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

gas/

	* config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw.
	(cpu_noarch): Add noavx512_4vnniw.
	* doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw.
	* testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests.
	* testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test.
	* testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
	CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_4VNNIW.
	* i386-opc.h (enum): (AVX512_4VNNIW): New.
	(i386_cpu_flags): Add cpuavx512_4vnniw.
	* i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
---
 gas/config/tc-i386.c                               |     3 +
 gas/doc/c-i386.texi                                |     6 +-
 gas/testsuite/gas/i386/avx512_4vnniw-intel.d       |    45 +
 gas/testsuite/gas/i386/avx512_4vnniw.d             |    45 +
 gas/testsuite/gas/i386/avx512_4vnniw.s             |    41 +
 gas/testsuite/gas/i386/avx512_4vnniw_vl-intel.d    |    79 +
 gas/testsuite/gas/i386/avx512_4vnniw_vl.d          |    79 +
 gas/testsuite/gas/i386/avx512_4vnniw_vl.s          |    75 +
 gas/testsuite/gas/i386/i386.exp                    |     8 +
 .../gas/i386/x86-64-avx512_4vnniw-intel.d          |    45 +
 gas/testsuite/gas/i386/x86-64-avx512_4vnniw.d      |    45 +
 gas/testsuite/gas/i386/x86-64-avx512_4vnniw.s      |    41 +
 .../gas/i386/x86-64-avx512_4vnniw_vl-intel.d       |    79 +
 gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d   |    79 +
 gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s   |    75 +
 opcodes/i386-dis-evex.h                            |    18 +-
 opcodes/i386-dis.c                                 |     2 +
 opcodes/i386-gen.c                                 |     7 +-
 opcodes/i386-init.h                                |   274 +-
 opcodes/i386-opc.h                                 |     3 +
 opcodes/i386-opc.tbl                               |    12 +
 opcodes/i386-tbl.h                                 | 10528 ++++++++++---------
 22 files changed, 6247 insertions(+), 5342 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/avx512_4vnniw-intel.d
 create mode 100644 gas/testsuite/gas/i386/avx512_4vnniw.d
 create mode 100644 gas/testsuite/gas/i386/avx512_4vnniw.s
 create mode 100644 gas/testsuite/gas/i386/avx512_4vnniw_vl-intel.d
 create mode 100644 gas/testsuite/gas/i386/avx512_4vnniw_vl.d
 create mode 100644 gas/testsuite/gas/i386/avx512_4vnniw_vl.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx512_4vnniw-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx512_4vnniw.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx512_4vnniw.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d2ec480..ca26127 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -964,6 +964,8 @@ static const arch_entry cpu_arch[] =
     CPU_AVX512VBMI_FLAGS, 0 },
   { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
     CPU_AVX512_4FMAPS_FLAGS, 0 },
+  { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
+    CPU_AVX512_4VNNIW_FLAGS, 0 },
   { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
     CPU_CLZERO_FLAGS, 0 },
   { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
@@ -1002,6 +1004,7 @@ static const noarch_entry cpu_noarch[] =
   { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
   { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
   { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
+  { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
 };
 
 #ifdef I386COFF
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 7aa043e..c3c632d 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -181,6 +181,7 @@ accept various extension mnemonics.  For example,
 @code{avx512ifma},
 @code{avx512vbmi},
 @code{avx512_4fmaps},
+@code{avx512_4vnniw},
 @code{noavx512f},
 @code{noavx512cd},
 @code{noavx512er},
@@ -191,6 +192,7 @@ accept various extension mnemonics.  For example,
 @code{noavx512ifma},
 @code{noavx512vbmi},
 @code{noavx512_4fmaps},
+@code{noavx512_4vnniw},
 @code{vmx},
 @code{vmfunc},
 @code{smx},
@@ -1192,8 +1194,8 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
-@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.clwb}
-@item @samp{.rdpid} @tab @samp{.ptwrite}
+@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
+@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw-intel.d b/gas/testsuite/gas/i386/avx512_4vnniw-intel.d
new file mode 100644
index 0000000..ba4299a
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw-intel.d
@@ -0,0 +1,45 @@
+#objdump: -dw -Mintel
+#name: i386 AVX512/4VNNIW insns (Intel disassembly)
+#source: avx512_4vnniw.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 09[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 4f 52 09[ 	]*vp4dpwssd zmm1\{k7\},zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f cf 52 09[ 	]*vp4dpwssd zmm1\{k7\}\{z\},zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a e0 0f 00 00[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a 00 10 00 00[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a 00 f0 ff ff[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a e0 ef ff ff[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 09[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 4f 53 09[ 	]*vp4dpwssds zmm1\{k7\},zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f cf 53 09[ 	]*vp4dpwssds zmm1\{k7\}\{z\},zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a e0 0f 00 00[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a 00 10 00 00[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a 00 f0 ff ff[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a e0 ef ff ff[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 09[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 09[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 4f 52 09[ 	]*vp4dpwssd zmm1\{k7\},zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f cf 52 09[ 	]*vp4dpwssd zmm1\{k7\}\{z\},zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a e0 0f 00 00[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a 00 10 00 00[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a 00 f0 ff ff[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a e0 ef ff ff[ 	]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 09[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 09[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 4f 53 09[ 	]*vp4dpwssds zmm1\{k7\},zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f cf 53 09[ 	]*vp4dpwssds zmm1\{k7\}\{z\},zmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a e0 0f 00 00[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a 00 10 00 00[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a 00 f0 ff ff[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a e0 ef ff ff[ 	]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx-0x1020\]
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw.d b/gas/testsuite/gas/i386/avx512_4vnniw.d
new file mode 100644
index 0000000..919f31e
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw.d
@@ -0,0 +1,45 @@
+#objdump: -dw
+#name: i386 AVX512/4VNNIW insns
+#source: avx512_4vnniw.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 09[ 	]*vp4dpwssd \(%ecx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 4f 52 09[ 	]*vp4dpwssd \(%ecx\),%zmm4,%zmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f cf 52 09[ 	]*vp4dpwssd \(%ecx\),%zmm4,%zmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 09[ 	]*vp4dpwssds \(%ecx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 4f 53 09[ 	]*vp4dpwssds \(%ecx\),%zmm4,%zmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f cf 53 09[ 	]*vp4dpwssds \(%ecx\),%zmm4,%zmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 09[ 	]*vp4dpwssd \(%ecx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 09[ 	]*vp4dpwssd \(%ecx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 4f 52 09[ 	]*vp4dpwssd \(%ecx\),%zmm4,%zmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f cf 52 09[ 	]*vp4dpwssd \(%ecx\),%zmm4,%zmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 09[ 	]*vp4dpwssds \(%ecx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 09[ 	]*vp4dpwssds \(%ecx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 4f 53 09[ 	]*vp4dpwssds \(%ecx\),%zmm4,%zmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f cf 53 09[ 	]*vp4dpwssds \(%ecx\),%zmm4,%zmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%edx\),%zmm4,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 48 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%edx\),%zmm4,%zmm1
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw.s b/gas/testsuite/gas/i386/avx512_4vnniw.s
new file mode 100644
index 0000000..a67d854
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw.s
@@ -0,0 +1,41 @@
+# Check 32bit AVX512_4VNNIW instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vp4dpwssd	(%ecx), %zmm4, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssd	(%ecx), %zmm4, %zmm1{%k7}	 # AVX512_4VNNIW
+	vp4dpwssd	(%ecx), %zmm4, %zmm1{%k7}{z}	 # AVX512_4VNNIW
+	vp4dpwssd	-123456(%esp,%esi,8), %zmm4, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssd	4064(%edx), %zmm4, %zmm1	 # AVX512_4VNNIW Disp8
+	vp4dpwssd	4096(%edx), %zmm4, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssd	-4096(%edx), %zmm4, %zmm1	 # AVX512_4VNNIW Disp8
+	vp4dpwssd	-4128(%edx), %zmm4, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssds	(%ecx), %zmm4, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssds	(%ecx), %zmm4, %zmm1{%k7}	 # AVX512_4VNNIW
+	vp4dpwssds	(%ecx), %zmm4, %zmm1{%k7}{z}	 # AVX512_4VNNIW
+	vp4dpwssds	-123456(%esp,%esi,8), %zmm4, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssds	4064(%edx), %zmm4, %zmm1	 # AVX512_4VNNIW Disp8
+	vp4dpwssds	4096(%edx), %zmm4, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssds	-4096(%edx), %zmm4, %zmm1	 # AVX512_4VNNIW Disp8
+	vp4dpwssds	-4128(%edx), %zmm4, %zmm1	 # AVX512_4VNNIW
+
+	.intel_syntax noprefix
+	vp4dpwssd	zmm1, zmm4, [ecx]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1, zmm4, XMMWORD PTR [ecx]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1{k7}, zmm4, XMMWORD PTR [ecx]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1{k7}{z}, zmm4, XMMWORD PTR [ecx]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1, zmm4, XMMWORD PTR [esp+esi*8-123456]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1, zmm4, XMMWORD PTR [edx+4064]	 # AVX512_4VNNIW Disp8
+	vp4dpwssd	zmm1, zmm4, XMMWORD PTR [edx+4096]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1, zmm4, XMMWORD PTR [edx-4096]	 # AVX512_4VNNIW Disp8
+	vp4dpwssd	zmm1, zmm4, XMMWORD PTR [edx-4128]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1, zmm4, [ecx]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1, zmm4, XMMWORD PTR [ecx]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1{k7}, zmm4, XMMWORD PTR [ecx]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1{k7}{z}, zmm4, XMMWORD PTR [ecx]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1, zmm4, XMMWORD PTR [esp+esi*8-123456]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1, zmm4, XMMWORD PTR [edx+4064]	 # AVX512_4VNNIW Disp8
+	vp4dpwssds	zmm1, zmm4, XMMWORD PTR [edx+4096]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1, zmm4, XMMWORD PTR [edx-4096]	 # AVX512_4VNNIW Disp8
+	vp4dpwssds	zmm1, zmm4, XMMWORD PTR [edx-4128]	 # AVX512_4VNNIW
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw_vl-intel.d b/gas/testsuite/gas/i386/avx512_4vnniw_vl-intel.d
new file mode 100644
index 0000000..a7d3ed9
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw_vl-intel.d
@@ -0,0 +1,79 @@
+#objdump: -dw -Mintel
+#name: i386 AVX512/4VNNIW_VL insns (Intel disassembly)
+#source: avx512_4vnniw_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 09[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 0f 52 09[ 	]*vp4dpwssd xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 8f 52 09[ 	]*vp4dpwssd xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a e0 0f 00 00[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a 00 10 00 00[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a 00 f0 ff ff[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a e0 ef ff ff[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 09[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 2f 52 09[ 	]*vp4dpwssd ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f af 52 09[ 	]*vp4dpwssd ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a e0 0f 00 00[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a 00 10 00 00[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a 00 f0 ff ff[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a e0 ef ff ff[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 09[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 0f 53 09[ 	]*vp4dpwssds xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 8f 53 09[ 	]*vp4dpwssds xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a e0 0f 00 00[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a 00 10 00 00[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a 00 f0 ff ff[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a e0 ef ff ff[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 09[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 2f 53 09[ 	]*vp4dpwssds ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f af 53 09[ 	]*vp4dpwssds ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a e0 0f 00 00[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a 00 10 00 00[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a 00 f0 ff ff[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a e0 ef ff ff[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 09[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 09[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 0f 52 09[ 	]*vp4dpwssd xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 8f 52 09[ 	]*vp4dpwssd xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a e0 0f 00 00[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a 00 10 00 00[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a 00 f0 ff ff[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a e0 ef ff ff[ 	]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 09[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 09[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 2f 52 09[ 	]*vp4dpwssd ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f af 52 09[ 	]*vp4dpwssd ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a e0 0f 00 00[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a 00 10 00 00[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a 00 f0 ff ff[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a e0 ef ff ff[ 	]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 09[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 09[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 0f 53 09[ 	]*vp4dpwssds xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 8f 53 09[ 	]*vp4dpwssds xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a e0 0f 00 00[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a 00 10 00 00[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a 00 f0 ff ff[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a e0 ef ff ff[ 	]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 09[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 09[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 2f 53 09[ 	]*vp4dpwssds ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f af 53 09[ 	]*vp4dpwssds ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a e0 0f 00 00[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a 00 10 00 00[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a 00 f0 ff ff[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a e0 ef ff ff[ 	]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw_vl.d b/gas/testsuite/gas/i386/avx512_4vnniw_vl.d
new file mode 100644
index 0000000..e796321
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw_vl.d
@@ -0,0 +1,79 @@
+#objdump: -dw
+#name: i386 AVX512/4VNNIW_VL insns
+#source: avx512_4vnniw_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 09[ 	]*vp4dpwssd \(%ecx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 0f 52 09[ 	]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 8f 52 09[ 	]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 09[ 	]*vp4dpwssd \(%ecx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 2f 52 09[ 	]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f af 52 09[ 	]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 09[ 	]*vp4dpwssds \(%ecx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 0f 53 09[ 	]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 8f 53 09[ 	]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 09[ 	]*vp4dpwssds \(%ecx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 2f 53 09[ 	]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f af 53 09[ 	]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 09[ 	]*vp4dpwssd \(%ecx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 09[ 	]*vp4dpwssd \(%ecx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 0f 52 09[ 	]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 8f 52 09[ 	]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 09[ 	]*vp4dpwssd \(%ecx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 09[ 	]*vp4dpwssd \(%ecx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 2f 52 09[ 	]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f af 52 09[ 	]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 09[ 	]*vp4dpwssds \(%ecx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 09[ 	]*vp4dpwssds \(%ecx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 0f 53 09[ 	]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 8f 53 09[ 	]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 08 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%edx\),%xmm4,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 09[ 	]*vp4dpwssds \(%ecx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 09[ 	]*vp4dpwssds \(%ecx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 2f 53 09[ 	]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f af 53 09[ 	]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%edx\),%ymm4,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5f 28 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%edx\),%ymm4,%ymm1
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw_vl.s b/gas/testsuite/gas/i386/avx512_4vnniw_vl.s
new file mode 100644
index 0000000..dfdd485
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw_vl.s
@@ -0,0 +1,75 @@
+# Check 32bit AVX512{_4VNNIW,VL} instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vp4dpwssd	(%ecx), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	(%ecx), %xmm4, %xmm1{%k7}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	(%ecx), %xmm4, %xmm1{%k7}{z}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	-123456(%esp,%esi,8), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	4064(%edx), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	4096(%edx), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	-4096(%edx), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	-4128(%edx), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	(%ecx), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	(%ecx), %ymm4, %ymm1{%k7}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	(%ecx), %ymm4, %ymm1{%k7}{z}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	-123456(%esp,%esi,8), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	4064(%edx), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	4096(%edx), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	-4096(%edx), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	-4128(%edx), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%ecx), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%ecx), %xmm4, %xmm1{%k7}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%ecx), %xmm4, %xmm1{%k7}{z}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	-123456(%esp,%esi,8), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	4064(%edx), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	4096(%edx), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	-4096(%edx), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	-4128(%edx), %xmm4, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%ecx), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%ecx), %ymm4, %ymm1{%k7}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%ecx), %ymm4, %ymm1{%k7}{z}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	-123456(%esp,%esi,8), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	4064(%edx), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	4096(%edx), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	-4096(%edx), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	-4128(%edx), %ymm4, %ymm1	 # AVX512{_4VNNIW,VL}
+
+	.intel_syntax noprefix
+	vp4dpwssd	xmm1, xmm4, [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1, xmm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1{k7}, xmm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1{k7}{z}, xmm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1, xmm4, XMMWORD PTR [esp+esi*8-123456]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1, xmm4, XMMWORD PTR [edx+4064]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	xmm1, xmm4, XMMWORD PTR [edx+4096]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1, xmm4, XMMWORD PTR [edx-4096]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	xmm1, xmm4, XMMWORD PTR [edx-4128]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1, ymm4, [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1, ymm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1{k7}, ymm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1{k7}{z}, ymm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1, ymm4, XMMWORD PTR [esp+esi*8-123456]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1, ymm4, XMMWORD PTR [edx+4064]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	ymm1, ymm4, XMMWORD PTR [edx+4096]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1, ymm4, XMMWORD PTR [edx-4096]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	ymm1, ymm4, XMMWORD PTR [edx-4128]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1, xmm4, [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1, xmm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1{k7}, xmm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1{k7}{z}, xmm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1, xmm4, XMMWORD PTR [esp+esi*8-123456]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1, xmm4, XMMWORD PTR [edx+4064]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	xmm1, xmm4, XMMWORD PTR [edx+4096]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1, xmm4, XMMWORD PTR [edx-4096]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	xmm1, xmm4, XMMWORD PTR [edx-4128]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1, ymm4, [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1, ymm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1{k7}, ymm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1{k7}{z}, ymm4, XMMWORD PTR [ecx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1, ymm4, XMMWORD PTR [esp+esi*8-123456]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1, ymm4, XMMWORD PTR [edx+4064]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	ymm1, ymm4, XMMWORD PTR [edx+4096]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1, ymm4, XMMWORD PTR [edx-4096]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	ymm1, ymm4, XMMWORD PTR [edx-4128]	 # AVX512{_4VNNIW,VL}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 89e132a..11c342a 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -363,6 +363,10 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "avx512_4fmaps_vl-intel"
     run_list_test "avx512_4fmaps-warn"
     run_list_test "avx512_4fmaps_vl-warn"
+    run_dump_test "avx512_4vnniw"
+    run_dump_test "avx512_4vnniw-intel"
+    run_dump_test "avx512_4vnniw_vl"
+    run_dump_test "avx512_4vnniw_vl-intel"
     run_dump_test "clzero"
     run_dump_test "disassem"
     run_dump_test "mwaitx-bdver4"
@@ -771,6 +775,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-avx512_4fmaps_vl-intel"
     run_list_test "x86-64-avx512_4fmaps-warn"
     run_list_test "x86-64-avx512_4fmaps_vl-warn"
+    run_dump_test "x86-64-avx512_4vnniw"
+    run_dump_test "x86-64-avx512_4vnniw-intel"
+    run_dump_test "x86-64-avx512_4vnniw_vl"
+    run_dump_test "x86-64-avx512_4vnniw_vl-intel"
     run_dump_test "x86-64-clzero"
     run_dump_test "x86-64-mwaitx-bdver4"
     run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw-intel.d b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw-intel.d
new file mode 100644
index 0000000..2165353
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw-intel.d
@@ -0,0 +1,45 @@
+#objdump: -dw -Mintel
+#name: x86_64 AVX512/4VNNIW insns (Intel disassembly)
+#source: x86-64-avx512_4vnniw.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 09[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 4f 52 09[ 	]*vp4dpwssd zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f cf 52 09[ 	]*vp4dpwssd zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a e0 0f 00 00[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a 00 10 00 00[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a 00 f0 ff ff[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a e0 ef ff ff[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 09[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 4f 53 09[ 	]*vp4dpwssds zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f cf 53 09[ 	]*vp4dpwssds zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a e0 0f 00 00[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a 00 10 00 00[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a 00 f0 ff ff[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a e0 ef ff ff[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 09[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 09[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 4f 52 09[ 	]*vp4dpwssd zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f cf 52 09[ 	]*vp4dpwssd zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a e0 0f 00 00[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a 00 10 00 00[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a 00 f0 ff ff[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a e0 ef ff ff[ 	]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 09[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 09[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 4f 53 09[ 	]*vp4dpwssds zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f cf 53 09[ 	]*vp4dpwssds zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a e0 0f 00 00[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a 00 10 00 00[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a 00 f0 ff ff[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a e0 ef ff ff[ 	]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.d b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.d
new file mode 100644
index 0000000..1938cfe
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.d
@@ -0,0 +1,45 @@
+#objdump: -dw
+#name: x86_64 AVX512/4VNNIW insns
+#source: x86-64-avx512_4vnniw.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 09[ 	]*vp4dpwssd \(%rcx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 4f 52 09[ 	]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f cf 52 09[ 	]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 09[ 	]*vp4dpwssds \(%rcx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 4f 53 09[ 	]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f cf 53 09[ 	]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 09[ 	]*vp4dpwssd \(%rcx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 09[ 	]*vp4dpwssd \(%rcx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 4f 52 09[ 	]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f cf 52 09[ 	]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 09[ 	]*vp4dpwssds \(%rcx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 09[ 	]*vp4dpwssds \(%rcx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 4f 53 09[ 	]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f cf 53 09[ 	]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%rdx\),%zmm8,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 48 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%rdx\),%zmm8,%zmm1
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.s b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.s
new file mode 100644
index 0000000..b4295f9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.s
@@ -0,0 +1,41 @@
+# Check 64bit AVX512_4VNNIW instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vp4dpwssd	(%rcx), %zmm8, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssd	(%rcx), %zmm8, %zmm1{%k7}	 # AVX512_4VNNIW
+	vp4dpwssd	(%rcx), %zmm8, %zmm1{%k7}{z}	 # AVX512_4VNNIW
+	vp4dpwssd	-123456(%rax,%r14,8), %zmm8, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssd	4064(%rdx), %zmm8, %zmm1	 # AVX512_4VNNIW Disp8
+	vp4dpwssd	4096(%rdx), %zmm8, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssd	-4096(%rdx), %zmm8, %zmm1	 # AVX512_4VNNIW Disp8
+	vp4dpwssd	-4128(%rdx), %zmm8, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssds	(%rcx), %zmm8, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssds	(%rcx), %zmm8, %zmm1{%k7}	 # AVX512_4VNNIW
+	vp4dpwssds	(%rcx), %zmm8, %zmm1{%k7}{z}	 # AVX512_4VNNIW
+	vp4dpwssds	-123456(%rax,%r14,8), %zmm8, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssds	4064(%rdx), %zmm8, %zmm1	 # AVX512_4VNNIW Disp8
+	vp4dpwssds	4096(%rdx), %zmm8, %zmm1	 # AVX512_4VNNIW
+	vp4dpwssds	-4096(%rdx), %zmm8, %zmm1	 # AVX512_4VNNIW Disp8
+	vp4dpwssds	-4128(%rdx), %zmm8, %zmm1	 # AVX512_4VNNIW
+
+	.intel_syntax noprefix
+	vp4dpwssd	zmm1, zmm8, [rcx]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1, zmm8, XMMWORD PTR [rcx]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1{k7}, zmm8, XMMWORD PTR [rcx]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1{k7}{z}, zmm8, XMMWORD PTR [rcx]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1, zmm8, XMMWORD PTR [rax+r14*8-123456]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1, zmm8, XMMWORD PTR [rdx+4064]	 # AVX512_4VNNIW Disp8
+	vp4dpwssd	zmm1, zmm8, XMMWORD PTR [rdx+4096]	 # AVX512_4VNNIW
+	vp4dpwssd	zmm1, zmm8, XMMWORD PTR [rdx-4096]	 # AVX512_4VNNIW Disp8
+	vp4dpwssd	zmm1, zmm8, XMMWORD PTR [rdx-4128]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1, zmm8, [rcx]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1, zmm8, XMMWORD PTR [rcx]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1{k7}, zmm8, XMMWORD PTR [rcx]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1{k7}{z}, zmm8, XMMWORD PTR [rcx]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1, zmm8, XMMWORD PTR [rax+r14*8-123456]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1, zmm8, XMMWORD PTR [rdx+4064]	 # AVX512_4VNNIW Disp8
+	vp4dpwssds	zmm1, zmm8, XMMWORD PTR [rdx+4096]	 # AVX512_4VNNIW
+	vp4dpwssds	zmm1, zmm8, XMMWORD PTR [rdx-4096]	 # AVX512_4VNNIW Disp8
+	vp4dpwssds	zmm1, zmm8, XMMWORD PTR [rdx-4128]	 # AVX512_4VNNIW
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d
new file mode 100644
index 0000000..d4a7a95
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d
@@ -0,0 +1,79 @@
+#objdump: -dw -Mintel
+#name: x86_64 AVX512/4VNNIW_VL insns (Intel disassembly)
+#source: x86-64-avx512_4vnniw_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 09[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 0f 52 09[ 	]*vp4dpwssd xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 8f 52 09[ 	]*vp4dpwssd xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a e0 0f 00 00[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a 00 10 00 00[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a 00 f0 ff ff[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a e0 ef ff ff[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 09[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 2f 52 09[ 	]*vp4dpwssd ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f af 52 09[ 	]*vp4dpwssd ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a e0 0f 00 00[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a 00 10 00 00[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a 00 f0 ff ff[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a e0 ef ff ff[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 09[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 0f 53 09[ 	]*vp4dpwssds xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 8f 53 09[ 	]*vp4dpwssds xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a e0 0f 00 00[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a 00 10 00 00[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a 00 f0 ff ff[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a e0 ef ff ff[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 09[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 2f 53 09[ 	]*vp4dpwssds ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f af 53 09[ 	]*vp4dpwssds ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a e0 0f 00 00[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a 00 10 00 00[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a 00 f0 ff ff[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a e0 ef ff ff[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 09[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 09[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 0f 52 09[ 	]*vp4dpwssd xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 8f 52 09[ 	]*vp4dpwssd xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a e0 0f 00 00[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a 00 10 00 00[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a 00 f0 ff ff[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a e0 ef ff ff[ 	]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 09[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 09[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 2f 52 09[ 	]*vp4dpwssd ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f af 52 09[ 	]*vp4dpwssd ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a e0 0f 00 00[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a 00 10 00 00[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a 00 f0 ff ff[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a e0 ef ff ff[ 	]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 09[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 09[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 0f 53 09[ 	]*vp4dpwssds xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 8f 53 09[ 	]*vp4dpwssds xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a e0 0f 00 00[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a 00 10 00 00[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a 00 f0 ff ff[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a e0 ef ff ff[ 	]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 09[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 09[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 2f 53 09[ 	]*vp4dpwssds ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f af 53 09[ 	]*vp4dpwssds ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a e0 0f 00 00[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a 00 10 00 00[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a 00 f0 ff ff[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a e0 ef ff ff[ 	]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d
new file mode 100644
index 0000000..df0f522
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d
@@ -0,0 +1,79 @@
+#objdump: -dw
+#name: x86_64 AVX512/4VNNIW_VL insns
+#source: x86-64-avx512_4vnniw_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 09[ 	]*vp4dpwssd \(%rcx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 0f 52 09[ 	]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 8f 52 09[ 	]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 09[ 	]*vp4dpwssd \(%rcx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 2f 52 09[ 	]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f af 52 09[ 	]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 09[ 	]*vp4dpwssds \(%rcx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 0f 53 09[ 	]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 8f 53 09[ 	]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 09[ 	]*vp4dpwssds \(%rcx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 2f 53 09[ 	]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f af 53 09[ 	]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 09[ 	]*vp4dpwssd \(%rcx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 09[ 	]*vp4dpwssd \(%rcx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 0f 52 09[ 	]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 8f 52 09[ 	]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 09[ 	]*vp4dpwssd \(%rcx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 09[ 	]*vp4dpwssd \(%rcx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 2f 52 09[ 	]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f af 52 09[ 	]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ 	]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a e0 0f 00 00[ 	]*vp4dpwssd 0xfe0\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a 00 10 00 00[ 	]*vp4dpwssd 0x1000\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a 00 f0 ff ff[ 	]*vp4dpwssd -0x1000\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 52 8a e0 ef ff ff[ 	]*vp4dpwssd -0x1020\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 09[ 	]*vp4dpwssds \(%rcx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 09[ 	]*vp4dpwssds \(%rcx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 0f 53 09[ 	]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 8f 53 09[ 	]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 08 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%rdx\),%xmm8,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 09[ 	]*vp4dpwssds \(%rcx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 09[ 	]*vp4dpwssds \(%rcx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 2f 53 09[ 	]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f af 53 09[ 	]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ 	]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a e0 0f 00 00[ 	]*vp4dpwssds 0xfe0\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a 00 10 00 00[ 	]*vp4dpwssds 0x1000\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a 00 f0 ff ff[ 	]*vp4dpwssds -0x1000\(%rdx\),%ymm8,%ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 3f 28 53 8a e0 ef ff ff[ 	]*vp4dpwssds -0x1020\(%rdx\),%ymm8,%ymm1
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s
new file mode 100644
index 0000000..5f1a046
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s
@@ -0,0 +1,75 @@
+# Check 64bit AVX512{_4VNNIW,VL} instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vp4dpwssd	(%rcx), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	(%rcx), %xmm8, %xmm1{%k7}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	(%rcx), %xmm8, %xmm1{%k7}{z}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	-123456(%rax,%r14,8), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	4064(%rdx), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	4096(%rdx), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	-4096(%rdx), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	-4128(%rdx), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	(%rcx), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	(%rcx), %ymm8, %ymm1{%k7}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	(%rcx), %ymm8, %ymm1{%k7}{z}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	-123456(%rax,%r14,8), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	4064(%rdx), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	4096(%rdx), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	-4096(%rdx), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	-4128(%rdx), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%rcx), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%rcx), %xmm8, %xmm1{%k7}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%rcx), %xmm8, %xmm1{%k7}{z}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	-123456(%rax,%r14,8), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	4064(%rdx), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	4096(%rdx), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	-4096(%rdx), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	-4128(%rdx), %xmm8, %xmm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%rcx), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%rcx), %ymm8, %ymm1{%k7}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	(%rcx), %ymm8, %ymm1{%k7}{z}	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	-123456(%rax,%r14,8), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	4064(%rdx), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	4096(%rdx), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	-4096(%rdx), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	-4128(%rdx), %ymm8, %ymm1	 # AVX512{_4VNNIW,VL}
+
+	.intel_syntax noprefix
+	vp4dpwssd	xmm1, xmm8, [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1, xmm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1{k7}, xmm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1{k7}{z}, xmm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1, xmm8, XMMWORD PTR [rax+r14*8-123456]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1, xmm8, XMMWORD PTR [rdx+4064]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	xmm1, xmm8, XMMWORD PTR [rdx+4096]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	xmm1, xmm8, XMMWORD PTR [rdx-4096]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	xmm1, xmm8, XMMWORD PTR [rdx-4128]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1, ymm8, [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1, ymm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1{k7}, ymm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1{k7}{z}, ymm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1, ymm8, XMMWORD PTR [rax+r14*8-123456]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1, ymm8, XMMWORD PTR [rdx+4064]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	ymm1, ymm8, XMMWORD PTR [rdx+4096]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssd	ymm1, ymm8, XMMWORD PTR [rdx-4096]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssd	ymm1, ymm8, XMMWORD PTR [rdx-4128]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1, xmm8, [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1, xmm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1{k7}, xmm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1{k7}{z}, xmm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1, xmm8, XMMWORD PTR [rax+r14*8-123456]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1, xmm8, XMMWORD PTR [rdx+4064]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	xmm1, xmm8, XMMWORD PTR [rdx+4096]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	xmm1, xmm8, XMMWORD PTR [rdx-4096]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	xmm1, xmm8, XMMWORD PTR [rdx-4128]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1, ymm8, [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1, ymm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1{k7}, ymm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1{k7}{z}, ymm8, XMMWORD PTR [rcx]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1, ymm8, XMMWORD PTR [rax+r14*8-123456]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1, ymm8, XMMWORD PTR [rdx+4064]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	ymm1, ymm8, XMMWORD PTR [rdx+4096]	 # AVX512{_4VNNIW,VL}
+	vp4dpwssds	ymm1, ymm8, XMMWORD PTR [rdx-4096]	 # AVX512{_4VNNIW,VL} Disp8
+	vp4dpwssds	ymm1, ymm8, XMMWORD PTR [rdx-4128]	 # AVX512{_4VNNIW,VL}
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index bc304c8..0f8327b 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -387,8 +387,8 @@ static const struct dis386 evex_table[][256] = {
     /* 50 */
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3852) },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3853) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -2005,6 +2005,20 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { "vrsqrt14s%XW",	{ XMScalar, VexScalar, EXxmm_mdq }, 0 },
   },
+  /* PREFIX_EVEX_0F3852 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vp4dpwssd",	{ XM, Vex, EXxmm }, 0 },
+  },
+  /* PREFIX_EVEX_0F3853 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vp4dpwssds",	{ XM, Vex, EXxmm }, 0 },
+  },
   /* PREFIX_EVEX_0F3858 */
   {
     { Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index c6b0fc8..56b3407 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1548,6 +1548,8 @@ enum
   PREFIX_EVEX_0F384D,
   PREFIX_EVEX_0F384E,
   PREFIX_EVEX_0F384F,
+  PREFIX_EVEX_0F3852,
+  PREFIX_EVEX_0F3853,
   PREFIX_EVEX_0F3858,
   PREFIX_EVEX_0F3859,
   PREFIX_EVEX_0F385A,
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index f8c24a4..eec3514 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -219,6 +219,8 @@ static initializer cpu_flag_init[] =
     "CPU_AVX512F_FLAGS|CpuAVX512VBMI" },
   { "CPU_AVX512_4FMAPS_FLAGS",
     "CPU_AVX512F_FLAGS|CpuAVX512_4FMAPS" },
+  { "CPU_AVX512_4VNNIW_FLAGS",
+    "CPU_AVX512F_FLAGS|CpuAVX512_4VNNIW" },
   { "CPU_L1OM_FLAGS",
     "unknown" },
   { "CPU_K1OM_FLAGS",
@@ -286,7 +288,7 @@ static initializer cpu_flag_init[] =
   { "CPU_ANY_AVX2_FLAGS",
     "CpuAVX2" },
   { "CPU_ANY_AVX512F_FLAGS",
-    "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512F" },
+    "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512F" },
   { "CPU_ANY_AVX512CD_FLAGS",
     "CpuAVX512CD" },
   { "CPU_ANY_AVX512ER_FLAGS",
@@ -305,6 +307,8 @@ static initializer cpu_flag_init[] =
     "CpuAVX512VBMI" },
   { "CPU_ANY_AVX512_4FMAPS_FLAGS",
     "CpuAVX512_4FMAPS" },
+  { "CPU_ANY_AVX512_4VNNIW_FLAGS",
+    "CpuAVX512_4VNNIW" },
 };
 
 static initializer operand_type_init[] =
@@ -509,6 +513,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuAVX512IFMA),
   BITFIELD (CpuAVX512VBMI),
   BITFIELD (CpuAVX512_4FMAPS),
+  BITFIELD (CpuAVX512_4VNNIW),
   BITFIELD (CpuMWAITX),
   BITFIELD (CpuCLZERO),
   BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 2f10a37..9f16c6c 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -194,6 +194,8 @@ enum
   CpuAVX512VBMI,
   /* Intel AVX-512 4FMAPS Instructions support required.  */
   CpuAVX512_4FMAPS,
+  /* Intel AVX-512 4VNNIW Instructions support required.  */
+  CpuAVX512_4VNNIW,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -318,6 +320,7 @@ typedef union i386_cpu_flags
       unsigned int cpuavx512ifma:1;
       unsigned int cpuavx512vbmi:1;
       unsigned int cpuavx512_4fmaps:1;
+      unsigned int cpuavx512_4vnniw:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index a186543..9ec09dc 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -5935,6 +5935,18 @@ v4fnmaddss, 3, 0xf2ab, None, 1, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|VexOpco
 
 // AVX512_4FMAPS instructions end
 
+// AVX512_4VNNIW instructions
+
+vp4dpwssd, 3, 0xf252, None, 1, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
+vp4dpwssd, 3, 0xf252, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
+vp4dpwssd, 3, 0xf252, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
+
+vp4dpwssds, 3, 0xf253, None, 1, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
+vp4dpwssds, 3, 0xf253, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
+vp4dpwssds, 3, 0xf253, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
+
+// AVX512_4VNNIW instructions
+
 // CLZERO instructions
 
 clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-- 
1.8.3.1

