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Re: [PATCH, RFC] Add support for choosing disassembler cpu in GDB for POWER.
- From: Pedro Alves <palves at redhat dot com>
- To: Peter Bergner <bergner at vnet dot ibm dot com>, Ulrich Weigand <uweigand at de dot ibm dot com>
- Cc: Alan Modra <amodra at gmail dot com>, gdb-patches at sourceware dot org, binutils <binutils at sourceware dot org>
- Date: Thu, 27 Oct 2016 10:40:41 +0100
- Subject: Re: [PATCH, RFC] Add support for choosing disassembler cpu in GDB for POWER.
- Authentication-results: sourceware.org; auth=none
- References: <20161012082525.3250910FDC3@oc8523832656.ibm.com> <email@example.com>
On 10/27/2016 01:04 AM, Peter Bergner wrote:
> On 10/12/16 3:25 AM, Ulrich Weigand wrote:
>> A platform-independent set_disassemble_options() (or whatever it is
>> called) command should probably reside in disasm.c, and be installed
>> via (a newly added) _initialize_disasm initializer routine there.
>> To get at the current gdbarch, you can use get_current_arch (). This
>> function should be rarely used, but the one place where it *is* fine
>> is exactly in top-level command implementation routines.
>> Another option might be to refactor the way disassembler options
>> output is done in opcodes, e.g. by having platform-specific code
>> only provide an array of tuples of option names and explanatory
>> strings, and move the actual printing to common code. Then those
>> arrays could be exported to and reused by GDB. (In particular,
>> there's really no way to do a completer without such information.)
> How about what I implemented below?
I couldn't quite get why you need so much power specific parsing
code in ppc-tdep.c, though. What would be necessary to be able to
move most of that set/show handling to the common code?
I also wonder if you really want to stick with
"set powerpc disassembler <cpu>" instead of
"set powerpc disassembler-options <options>".
I.e., I wonder about making the power one defined exactly like:
"like 'set disassembler-options', but sets power disassembler
options even if the current arch is not power."
> On 10/12/16 2:35 PM, Pedro Alves wrote:
>> On 10/11/2016 07:48 PM, Peter Bergner wrote:
>>> I'm fine going with whatever option name people prefer. If you want
>>> "disassembler-options" instead of just "disassembler", ok, but shouldn't
>>> ARM be renamed then as well if it uses this mechanism?
>> I think so. That wouldn't break anyone's scripts, since "disassembler"
>> is an unambiguous prefix of "disassembler-options", and thus gdb
>> would still accept "disassembler".
> I had a look at ARM's use of "set disassembler". It isnt' what I thought
> it was. ARM doesn't have a way to change its disassembler cpu (ala -mcpu=...
> gas option) anymore than ppc couldn't before this patch. What ARM's
> "set disassembler" is setting is the disassembly style, which I think
> is similar to x86's "set disassembly-flavor" command. When you said
> that ARM could use this, were you speaking about adding new support
> for changing the disassembler cpu like we're doing here for ppc or
> did you want it to set the style using this generic hook?
The idea was to define the new command as exposing objdump's -M option:
-M, --disassembler-options=OPT Pass text OPT on to the disassembler
It happens that on power that allows only changing the cpu. Whereas
for ARM that tweaks other things. x86 has options for both cpu and
syntax. See what an --enable-targets=all build of
objdump says in its --help:
The following ARM specific disassembler options are supported for use with
the -M switch:
reg-names-special-atpcs Select special register names used in the ATPCS
reg-names-atpcs Select register names used in the ATPCS
reg-names-apcs Select register names used in the APCS
reg-names-std Select register names used in ARM's ISA documentation
reg-names-gcc Select register names used by GCC
reg-names-raw Select raw register names
force-thumb Assume all insns are Thumb insns
no-force-thumb Examine preceding label to determine an insn's type
The following PPC specific disassembler options are supported for use with
the -M switch:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455,
750cl, 821, 850, 860, a2, altivec, any, booke, booke32, cell, com,
e200z4, e300, e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, power4,
power5, power6, power7, power8, power9, ppc, ppc32, ppc64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx,
spe, titan, vle, vsx, htm, 32, 64
The following i386/x86-64 specific disassembler options are supported for use
with the -M switch (multiple options should be separated by commas):
x86-64 Disassemble in 64bit mode
i386 Disassemble in 32bit mode
i8086 Disassemble in 16bit mode
att Display instruction in AT&T syntax
intel Display instruction in Intel syntax
Display instruction in AT&T mnemonic
Display instruction in Intel mnemonic
addr64 Assume 64bit address size
addr32 Assume 32bit address size
addr16 Assume 16bit address size
data32 Assume 32bit data size
data16 Assume 16bit data size
suffix Always display instruction suffix in AT&T syntax
amd64 Display instruction in AMD64 ISA
intel64 Display instruction in Intel64 ISA
... and more for other archs.